ES9039Q2M S/PDIF DAC design

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#84
Minimizing close-in phase noise is similar to any effort of optimization. At some point the costs vs. gains cannot be justified. There is no guarantee that with ES9039Q2M in ASR mode clocks having lower close-in phase noise than e.g. Kyocera KC7050 would make such an audible difference that it could be reliably identified in controlled listening test. Same goes with synchronous mode. So far there are no studies or controlled listening tests showing audible difference between well implemented and well measuring DACs or clocks having low vs. ultra low close-in phase noise.
 
#85
Markw4 said:
Close-in phase noise is a different consideration from slow frequency drift.
Click to expand...

Yes - one causes analog pitch change - you need a pretty good music ear to catch that 😉 (read impossible) - but the other one....

Explain again how the close-in noise effects the listening experience for you?

And let's repeat how such noise, say -80...-100 (dBc/Hz) at 1...10 Hz, technically manifest itself on the analog side - i.e. the output of a DAC:

  • is noise added (i.e non harmonic additions)? How and how much?
  • is distortion added (i.e harmonic additions)? How and how much?
  • is FR changed? How and how much?
  • is phase changed? How and how much?
  • any other relevant analog signal characteristic I missed?

tnx!

//
 
#89
altor said:
Why not use synchronous mode?
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My board was configured in ASYNC not by myself, and just thought about to compare it now. If I want to put external 45.15/49.152 MCLK which HW right mode should i choose, #8? What does it mean #11 SYNC and ACG ?
esssync.jpg
 
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#90
TNT said:
  • any other relevant analog signal characteristic I missed?
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Yes. Pretty much everything that matters. This stuff and the preset state of the art in dac measurements has been discussed many times, including with links to and or attached scientific papers. For one example, the present state of the art does not include a good, standardized way to measure sound stage. I am not going to repeat the whole body of literature and discussions here. If someone wants to discuss some particular issue they would be welcome to PM.
 
#93
There is, "Objective assessment of phantom images in a 3-D sound field using a virtual listener," by Hawksford. There is other published research on localization cues as well. What we have is some of what we need for comprehensive objective measurements of sound stage. There is more work to be done, is all.
 
#96
Hello, finally my PCBs arrived and I had time to solder the components.

KH-AmpV3_06.png


Pro: Class A amplifier and TPA6120 work as expected with analogue input
Con: So far I didn't get the DAC to work :-(

Voltages are as following:

Avcc_dac1: 3,21V
Avcc_dac2: 3,21V
Vcca: 3,43V
Avdd: 3,40V
Clocksply1: 3,56V
Clocksply1: 3,57V

At the moment I only have an 25MHz Picoscope here, so the pule form of Clock1 and 2 can not be measured correctly but the output seems to be 3,3V for both of them.

As seen in the schematic I use a FCR684208R as the Toslink receiver, the first one seemed to be faulty, I measured a constant voltage of 4,3V at the output (regardless of the input signal)

I switched the component, this signal seems to be better:

20250525_spdif.png



Also no output of the DAC, I tried HW modes #16-18 with both clocks and mute with Pull 1 and 1.
Although I didn't find a clear statement of the SPDIF input voltage, I guessed that the voltage may be too high, so I used a voltage converter to reduce it:


20250525_spdif-0002.png


Still no luck.. Have I fried the ES9039? Are there any other ideas what to test? I also ordered the amanero to have an IIS input device, but it hasn't arrived yet.
 
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#97
Can you borrow a faster scope to accurately check all digital signals, and double check all DVM voltage readings?

Otherwise, the only way to troubleshoot further might be to connect by I2C bus to look at the registers.

Regarding the SPDIF input voltage it should probably be standard LVCMOS levels, or whatever is listed in the datasheet.
 
#98
florian911 said:
so I used a voltage converter to reduce it
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ES9039Q2M datasheet specifies that high-level I/O input voltage is AVDD/2+0.4 (=2.1V). So your reduced SPDIF input voltage is too low. Datasheet does not specify max I/O input voltage but in the older ES9038Q2M GPIO pins are 5V tolerant.

You should be able to reduce the SPDIF voltage to e.g. 3.3V just by lowering the power supply of the Toslink receiver.
 
#99
Markw4 said:
Can you borrow a faster scope to accurately check all digital signals, and double check all DVM voltage readings?
Otherwise, the only way to troubleshoot further might be to connect by I2C bus to look at the registers.
Click to expand...
The power supply levels were checked with DVM and scope, the only line which is too fast is the clock, right? I could access a faster scope, but not immediately.
Ok, I will get the esp32 running (not done yet).

bohrok2610 said:
Datasheet does not specify max I/O input voltage but in the older ES9038Q2M GPIO pins are 5V tolerant.

You should be able to reduce the SPDIF voltage to e.g. 3.3V just by lowering the power supply of the Toslink receiver.
Click to expand...
Hopefully this is true for the 9039 also.. Thanks I will try that (but guess it should than have worked also with the 5V level).
 
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