Note that when using non-audio oscillators, jitter is determined more by the PLL than by the oscillators.
Alex.
Alex.
I mean a frequency that is not a multiple of sampling. BTW this oscillators are proposed for audio by manufacturer,
Close-in phase noise is a different consideration from slow frequency drift. It is the close-in phase noise that Andrea Mori and others were trying to minimize.
Minimizing close-in phase noise is similar to any effort of optimization. At some point the costs vs. gains cannot be justified. There is no guarantee that with ES9039Q2M in ASR mode clocks having lower close-in phase noise than e.g. Kyocera KC7050 would make such an audible difference that it could be reliably identified in controlled listening test. Same goes with synchronous mode. So far there are no studies or controlled listening tests showing audible difference between well implemented and well measuring DACs or clocks having low vs. ultra low close-in phase noise.
Close-in phase noise is a different consideration from slow frequency drift.
Yes - one causes analog pitch change - you need a pretty good music ear to catch that 😉 (read impossible) - but the other one....
Explain again how the close-in noise effects the listening experience for you?
And let's repeat how such noise, say -80...-100 (dBc/Hz) at 1...10 Hz, technically manifest itself on the analog side - i.e. the output of a DAC:
- is noise added (i.e non harmonic additions)? How and how much?
- is distortion added (i.e harmonic additions)? How and how much?
- is FR changed? How and how much?
- is phase changed? How and how much?
- any other relevant analog signal characteristic I missed?
tnx!
//
I mean the same.I mean a frequency that is not a multiple of sampling.
Alex.
Thanks, now understand. So, I have two sources, SA9227 (with 45.158 and 49.152Mhz NSC5083D) and XU208 (with 22.5792 and 24.576 same model XOs) and will have an opportunity in a few weeks to compare them as MCLK with ASR mode on oscillators at non-audio frequencies.I mean the same.
My board was configured in ASYNC not by myself, and just thought about to compare it now. If I want to put external 45.15/49.152 MCLK which HW right mode should i choose, #8? What does it mean #11 SYNC and ACG ?Why not use synchronous mode?
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Yes. Pretty much everything that matters. This stuff and the preset state of the art in dac measurements has been discussed many times, including with links to and or attached scientific papers. For one example, the present state of the art does not include a good, standardized way to measure sound stage. I am not going to repeat the whole body of literature and discussions here. If someone wants to discuss some particular issue they would be welcome to PM.
- any other relevant analog signal characteristic I missed?
As has been discussed before sound stage is a subjective illusion. Typically such illusions or anything else subjective are impossible to measure.For one example, the present state of the art does not include a good, standardized way to measure sound stage.
There is, "Objective assessment of phantom images in a 3-D sound field using a virtual listener," by Hawksford. There is other published research on localization cues as well. What we have is some of what we need for comprehensive objective measurements of sound stage. There is more work to be done, is all.
Note that virtual listener is not human. So your subjective claims regarding sound stage do not apply.
Yes, SPDIF is better to use in ASync mode, but he mentioned XMOS, which is for USB, and in this case Sync is usually better.This thread is about SPDIF.
Alex.
P.S. When I made DACs with ESS, I used Async for SPDIF/Toslink/Bluetooth, and Sync for USB.
Hello, finally my PCBs arrived and I had time to solder the components.
Pro: Class A amplifier and TPA6120 work as expected with analogue input
Con: So far I didn't get the DAC to work :-(
Voltages are as following:
Avcc_dac1: 3,21V
Avcc_dac2: 3,21V
Vcca: 3,43V
Avdd: 3,40V
Clocksply1: 3,56V
Clocksply1: 3,57V
At the moment I only have an 25MHz Picoscope here, so the pule form of Clock1 and 2 can not be measured correctly but the output seems to be 3,3V for both of them.
As seen in the schematic I use a FCR684208R as the Toslink receiver, the first one seemed to be faulty, I measured a constant voltage of 4,3V at the output (regardless of the input signal)
I switched the component, this signal seems to be better:
Also no output of the DAC, I tried HW modes #16-18 with both clocks and mute with Pull 1 and 1.
Although I didn't find a clear statement of the SPDIF input voltage, I guessed that the voltage may be too high, so I used a voltage converter to reduce it:
Still no luck.. Have I fried the ES9039? Are there any other ideas what to test? I also ordered the amanero to have an IIS input device, but it hasn't arrived yet.
Pro: Class A amplifier and TPA6120 work as expected with analogue input
Con: So far I didn't get the DAC to work :-(
Voltages are as following:
Avcc_dac1: 3,21V
Avcc_dac2: 3,21V
Vcca: 3,43V
Avdd: 3,40V
Clocksply1: 3,56V
Clocksply1: 3,57V
At the moment I only have an 25MHz Picoscope here, so the pule form of Clock1 and 2 can not be measured correctly but the output seems to be 3,3V for both of them.
As seen in the schematic I use a FCR684208R as the Toslink receiver, the first one seemed to be faulty, I measured a constant voltage of 4,3V at the output (regardless of the input signal)
I switched the component, this signal seems to be better:
Also no output of the DAC, I tried HW modes #16-18 with both clocks and mute with Pull 1 and 1.
Although I didn't find a clear statement of the SPDIF input voltage, I guessed that the voltage may be too high, so I used a voltage converter to reduce it:
Still no luck.. Have I fried the ES9039? Are there any other ideas what to test? I also ordered the amanero to have an IIS input device, but it hasn't arrived yet.
Can you borrow a faster scope to accurately check all digital signals, and double check all DVM voltage readings?
Otherwise, the only way to troubleshoot further might be to connect by I2C bus to look at the registers.
Regarding the SPDIF input voltage it should probably be standard LVCMOS levels, or whatever is listed in the datasheet.
Otherwise, the only way to troubleshoot further might be to connect by I2C bus to look at the registers.
Regarding the SPDIF input voltage it should probably be standard LVCMOS levels, or whatever is listed in the datasheet.
ES9039Q2M datasheet specifies that high-level I/O input voltage is AVDD/2+0.4 (=2.1V). So your reduced SPDIF input voltage is too low. Datasheet does not specify max I/O input voltage but in the older ES9038Q2M GPIO pins are 5V tolerant.so I used a voltage converter to reduce it
You should be able to reduce the SPDIF voltage to e.g. 3.3V just by lowering the power supply of the Toslink receiver.
The power supply levels were checked with DVM and scope, the only line which is too fast is the clock, right? I could access a faster scope, but not immediately.Can you borrow a faster scope to accurately check all digital signals, and double check all DVM voltage readings?
Otherwise, the only way to troubleshoot further might be to connect by I2C bus to look at the registers.
Ok, I will get the esp32 running (not done yet).
Hopefully this is true for the 9039 also.. Thanks I will try that (but guess it should than have worked also with the 5V level).Datasheet does not specify max I/O input voltage but in the older ES9038Q2M GPIO pins are 5V tolerant.
You should be able to reduce the SPDIF voltage to e.g. 3.3V just by lowering the power supply of the Toslink receiver.
Status update, a bit of success:
After not getting a signal on the SCL line I tested with an I2C component which I knew was working I found out that my esp32 had an issue on GPIO 22, after changing SCL to GPIO 23 I got a response and the DAC was found at adress 0x49 with a standard I2C scan (0x92 acc the 8 bit version in the datasheet).
before (blue = SDA):
after changing I2C pin for SCL:
A register dump got me all registers, I set everything which seemed be connected to S/PDIF in the datasheet accordingly. I wrote these registers (ESP32 in Arduino IDE), does this seem to make sense? Unfortunately I can not test with audio at the moment because I don't have a working Toslink converter, they seem to be very sensible when hand soldering..
Here is the code, probably nothing new for you guys but maybe someone can use it in the future:
After not getting a signal on the SCL line I tested with an I2C component which I knew was working I found out that my esp32 had an issue on GPIO 22, after changing SCL to GPIO 23 I got a response and the DAC was found at adress 0x49 with a standard I2C scan (0x92 acc the 8 bit version in the datasheet).
before (blue = SDA):
after changing I2C pin for SCL:
A register dump got me all registers, I set everything which seemed be connected to S/PDIF in the datasheet accordingly. I wrote these registers (ESP32 in Arduino IDE), does this seem to make sense? Unfortunately I can not test with audio at the moment because I don't have a working Toslink converter, they seem to be very sensible when hand soldering..
Here is the code, probably nothing new for you guys but maybe someone can use it in the future:
C++:
#include <Wire.h>
#define I2C_ADDRESS 0x49
#define I2C_SDA 21
#define I2C_SCL 23
void setup() {
Serial.begin(115200);
Wire.begin(I2C_SDA, I2C_SCL);
Wire.setClock(100000); // Set I2C clock frequency
delay(1000); // Wait for DAC to power up and initialize
// Register 0: SYSTEM CONFIG (default 0b00000000)
// Set DAC_MODE (bit 1) to enable DAC analog output
// New value: 0x02 (0b00000010)
writeRegister(0x00, 0x02);
// Register 1: SYS MODE CONFIG (default 0b10110001)
// Enable SPDIF decode (bit 3 = 1), keep other defaults
// New value: 0x89 (0b10001001)
writeRegister(0x01, 0x89);
// Register 42: GPIO INPUT ENABLE (default 0b00000000)
// Enable GPIO4_SDB (bit 3 = 1)
// New value: 0x08 (0b00001000)
writeRegister(0x2A, 0x08);
// Register 57: INPUT SELECTION (default 0b01000000)
// Manual input select (AUTO_INPUT_SEL = 0), select S/PDIF (INPUT_SEL = 0b11)
// New value: 0x46 (0b01000110)
writeRegister(0x39, 0x46);
// Register 86: DAC MUTE (default 0b00000000)
// Leave mute disabled
// New value: 0x00 (0b00000000)
writeRegister(0x56, 0x00);
// Register 89: IIR BANDWIDTH & SPDIF SELECT (default 0b00000100)
// SPDIF_SEL = GPIO4 (bits 7:4 = 0b0110), IIR_BW = 0b100 (default), VOLUME_HOLD = 0
// New value: 0x64 (0b01100100)
writeRegister(0x59, 0x64);
// Register 123: AUTOMUTE ENABLE (default 0b11111111)
// Disable automute (bits 1:0 = 0)
// New value: 0x00 (0b00000000)
writeRegister(0x7B, 0x00);
// Register 136: SPDIF_DATA_SEL (default 0b00000000)
// Select byte 0 of SPDIF payload
// New value: 0x00 (0b00000000)
writeRegister(0x88, 0x00);
Serial.println("DAC configured for S/PDIF input on GPIO4.");
}
void loop() {
// Register 245: INPUT STREAM READBACK
// Bit 4 = SPDIF_VALID
uint8_t inputStream;
if (readRegister(0xF5, &inputStream)) {
bool spdifValid = (inputStream >> 4) & 0x01;
Serial.print("S/PDIF Valid: ");
Serial.println(spdifValid ? "YES" : "NO");
}
// Register 251: SPDIF_DATA_READ
// Read byte 0 of the SPDIF payload
uint8_t spdifByte;
if (readRegister(0xFB, &spdifByte)) {
Serial.print("S/PDIF Byte 0: 0x");
Serial.println(spdifByte, HEX);
}
delay(1000);
}
bool writeRegister(uint8_t reg, uint8_t value) {
Wire.beginTransmission(I2C_ADDRESS);
Wire.write(reg);
Wire.write(value);
return Wire.endTransmission() == 0;
}
bool readRegister(uint8_t reg, uint8_t *value) {
Wire.beginTransmission(I2C_ADDRESS);
Wire.write(reg);
if (Wire.endTransmission(false) != 0) return false;
if (Wire.requestFrom(I2C_ADDRESS, 1) == 1) {
*value = Wire.read();
return true;
}
return false;
}
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