AndrewT said:
not according to Bateman's "Capacitor Sound" series, his high resolution distortion measurements of electrolytic caps showed reduced distortion for the nonpolars with fully formed oxide layers on both foils compared to all other configurations; including the use of polarizing V with back to back polar caps
nonpolars with fully formed oxide layers on both foils are measureably superior
Also better with a low feedback design to use non-polar because the cap bias is going to be all over the place. With a high feedback design with bipolar LTP the base current can just about keep the cap biased in one polarity enough because the feedback signal modulation is tiny; some prefer solid tantalum with such small bias.
Jeez, what a can of worms I opened here! Maybe I should just go fishin'!
I wouldn't even use a cap if I could knock down the initial offset to ~150mV's.
Anyone have any idea's about the real issue I am trying to solve for?
Thanks, Don
I wouldn't even use a cap if I could knock down the initial offset to ~150mV's.
Anyone have any idea's about the real issue I am trying to solve for?
Thanks, Don
The worms are everywhere in performance audio!
Let me get the facts clear. You see about 600mV offset at power up and this declines to a happy 20mV after some minutes?
So if you don't want to control it out you are going to have to find out which transistor is the culprit. It's a little tough to estimate the thermal sensitivities by eyeing your schematic, but it will be one or more of Q1, Q2, Q3, Q6, Q4. I imagine Q1 & Q2 are near each other and you've hand matched them so they are least likely to be the culprit. You'll then have to devise some thermal compensation. If you have a hairdryer you may be able to roughly identify the most sensitive circuit. That's the best I can suggest without a simulation model.
By the way, what is C20 for?
Let me get the facts clear. You see about 600mV offset at power up and this declines to a happy 20mV after some minutes?
So if you don't want to control it out you are going to have to find out which transistor is the culprit. It's a little tough to estimate the thermal sensitivities by eyeing your schematic, but it will be one or more of Q1, Q2, Q3, Q6, Q4. I imagine Q1 & Q2 are near each other and you've hand matched them so they are least likely to be the culprit. You'll then have to devise some thermal compensation. If you have a hairdryer you may be able to roughly identify the most sensitive circuit. That's the best I can suggest without a simulation model.
By the way, what is C20 for?
traderbam said:
Thanks for the suggestions on tracking the offset issue. You are correct and Q1, 2 are closely matched and bolted tab to tab. I think Q6 might be the wildcard here. I am thinking of running the LTP with just a little more current which should make Q6 pass a little more current and make the output a little more positive. Thoughts?
C20 was necessary to keep the amp from oscillating. Using just C21 didn't do it.
Thanks, Don
Don,
Running more LTP current may change things a little and give a higher, stable offset. My concern is that the extra current may also give you a higher turn-on offset so it may not help. What I think you need to do is reduce the change in offset as the transistors change their temperatures.
I wonder why R2 != R16. If they did then the temperature change in Q4 & Q6, provided their gate thresholds and Gm change similarly, would change their Id but not unbalance the LTP. However, even if R2 = R16 any change in Q3 Id will unbalance the LTP. With Q6 fed single-ended from the LTP is really important to keep the LTP tail current stable. If this is the problem then it is relatively easy to deal with.
I confess I'm a little concerned about C20 as a stability band-aid. I may be wrong but I predict the amp may only be marginally stable. You'll have to test it well.
One thing at a time. 😎
Brian
Running more LTP current may change things a little and give a higher, stable offset. My concern is that the extra current may also give you a higher turn-on offset so it may not help. What I think you need to do is reduce the change in offset as the transistors change their temperatures.
I wonder why R2 != R16. If they did then the temperature change in Q4 & Q6, provided their gate thresholds and Gm change similarly, would change their Id but not unbalance the LTP. However, even if R2 = R16 any change in Q3 Id will unbalance the LTP. With Q6 fed single-ended from the LTP is really important to keep the LTP tail current stable. If this is the problem then it is relatively easy to deal with.
I confess I'm a little concerned about C20 as a stability band-aid. I may be wrong but I predict the amp may only be marginally stable. You'll have to test it well.
One thing at a time. 😎
Brian
Hi Trader,
why should R2=R16?
As I see it the three LEDs & R16 set Q4 quiescent current and that flows through Q6 as well.
R2 is passing both Q6 current and Q2 current. It's value is dependant on R1 and the ratio of currents flowing through iQ1=iQ2/iQ6.
However, a 1k pot across R16 (which could be changed to 110r or 120r to obtain the range of adjustment required) would allow fine trimming of output offset.
I would scrap the 100r and 39r2 degeneration resistors and replace with two accurately matched but separate 22r feeding direct to the drain of Q3.
why should R2=R16?
As I see it the three LEDs & R16 set Q4 quiescent current and that flows through Q6 as well.
R2 is passing both Q6 current and Q2 current. It's value is dependant on R1 and the ratio of currents flowing through iQ1=iQ2/iQ6.
However, a 1k pot across R16 (which could be changed to 110r or 120r to obtain the range of adjustment required) would allow fine trimming of output offset.
I would scrap the 100r and 39r2 degeneration resistors and replace with two accurately matched but separate 22r feeding direct to the drain of Q3.
Hi Andrew,
Good question. This is what I'm thinking. Imagine the cirucit has been powered up for a while and the dc operating points are stable. Now, imagine the temperature of the whole circuit changes. Assume the LED voltages don't change for the moment.
Suppose Q4's Vth decreases, this will increase Vs and the Id will increase by delta Vs divided by R16. To maintain the output dc offset Id of Q6 will have to change by the same amount. If the Q6 circuit was not affected by temperature, this Q6 Id change would have to be achieved by a change in Q6 Vg - thus unbalancing the LTP. However, if Q6 is affected the same way as Q4 then if R2 has the same value as R16, Q6 Vg stays the same. Does that make sense?
This won't exactly balance unless the sensitivities of Q4 and Q6 to temperature are the same. It also won't work if the voltage across LEDs 4-5 changes with temperature. So it won't work! But it may reduce the drift. Your idea of a pot across R16 (or it could be R2) would make it easier to find the optimum ratio of R2/R16 that minimizes thermal influence on Q6 Vg.
Are you concerned about other things related to P1?
Brian
Good question. This is what I'm thinking. Imagine the cirucit has been powered up for a while and the dc operating points are stable. Now, imagine the temperature of the whole circuit changes. Assume the LED voltages don't change for the moment.
Suppose Q4's Vth decreases, this will increase Vs and the Id will increase by delta Vs divided by R16. To maintain the output dc offset Id of Q6 will have to change by the same amount. If the Q6 circuit was not affected by temperature, this Q6 Id change would have to be achieved by a change in Q6 Vg - thus unbalancing the LTP. However, if Q6 is affected the same way as Q4 then if R2 has the same value as R16, Q6 Vg stays the same. Does that make sense?
This won't exactly balance unless the sensitivities of Q4 and Q6 to temperature are the same. It also won't work if the voltage across LEDs 4-5 changes with temperature. So it won't work! But it may reduce the drift. Your idea of a pot across R16 (or it could be R2) would make it easier to find the optimum ratio of R2/R16 that minimizes thermal influence on Q6 Vg.
It's pretty difficult to "balance" an LTP. One would like Q1 Vth and Q2 Vth to be the same and Q1 gm and Q2 gm to be the same. P1 will change the Id balance. Which will affect both. The danger is that if P1 is used to zero the output dc offset one could end up forcing the LTP out of balance too far. Better to fix the stage that is causing the offset.
Are you concerned about other things related to P1?
Brian
or use a DC servo to correct the current in Q4 to maintain low output offset. What would this circut look like and where would it inject the error correction?
If Q4 and Q6 share a large sink to keep them at the same temperature and minimise temperature variation, does that help output offset stability?
If Q4 and Q6 share a large sink to keep them at the same temperature and minimise temperature variation, does that help output offset stability?
that is why the LTP must be designed and built in balance. Allowing adjustment to unbalance it is plain wrong.
Andrew and Brian, also others, I included a way to balance the LTP in case I could not get a closely matched pair. The value of R2 was determined with the value of P1 exactly in the middle of its range. This is where it is right now. The measured current imbalance in the LTP is ~0.0003A. So we have a closely matched LTP. I believe that Q6 is the wild card in this equation. It will never inversely match Q4's characteristics, even if the source resistors are the same. I might be able to solve the issue thermally, as we know that the current through the devices increase with heat. First limit the temp rise, bigger heat sink for Q4 and Q6. That should mean less change in warm-up. Since the heat sink and devices are all equal in temp at turn on and we have a negative offset, decrease R2 slightly until the turn on balance is acceptable. Have a larger heat sink on Q6, for less positive drift.
This is my idea anyway. Thoughts, Ideas!
Thanks, Don
This is my idea anyway. Thoughts, Ideas!
Thanks, Don
Roender made an interesting comment here:
AndrewT agreed emphatically.
How much additional noise would this really contribute?
If you were able to double the shunt and series feedback resistors from 1K to 2K and 25K to 50K respectively, thus reducing by half the size of the shunt cap, would this increase noise by much? This is series, Johnson noise, no?
Given a gain around 28dB and speakers of 92db/watt/metre, would this greatly increase hiss? By how much? 6dB, 2dB, 0.3dB?
And what would be the effect of increasing the source resistance powering the feedback node?
Hugh
AndrewT agreed emphatically.
How much additional noise would this really contribute?
If you were able to double the shunt and series feedback resistors from 1K to 2K and 25K to 50K respectively, thus reducing by half the size of the shunt cap, would this increase noise by much? This is series, Johnson noise, no?
Given a gain around 28dB and speakers of 92db/watt/metre, would this greatly increase hiss? By how much? 6dB, 2dB, 0.3dB?
And what would be the effect of increasing the source resistance powering the feedback node?
Hugh
After degeneration LTP resistors, if you use some, that series resistor is main noise generator. I do not know how to quantify those things ...
Until the additional noise is quantified, and then checked subjectively with otherwise identical designs, then comments about reducing fb impedance to the lowest possible value are merely speculation. Spice might help here, but my personal subjective view, having done the experiment, is that any additional noise is insignificant in the overall noise of the amplifier and that a high impedance feedback network is not the bogeyman imagined here.
In fact it could have advantages in other areas, aside from reducing the value of the shunt cap...
Cheers,
Hugh
In fact it could have advantages in other areas, aside from reducing the value of the shunt cap...
Cheers,
Hugh
Hi Hugh,
You have just voiced the same concerns I have had about this issue. I believe a higher impedance is helpful for a few reasons. I don't think the noise contribution is that great a deal in a power amplifier. Possibly in a microphone stage or like circuit.
It is one way of getting a low DC offset on a single BJT diff pair type amplifier. There are more ways to achieve that.
I have seen feedback resistors burn out. A higher dissipation part would still get warm and possibly change it's value.
-Chris
You have just voiced the same concerns I have had about this issue. I believe a higher impedance is helpful for a few reasons. I don't think the noise contribution is that great a deal in a power amplifier. Possibly in a microphone stage or like circuit.
It is one way of getting a low DC offset on a single BJT diff pair type amplifier. There are more ways to achieve that.
I have seen feedback resistors burn out. A higher dissipation part would still get warm and possibly change it's value.
-Chris
Sorry if this is a bit offtopic, but here goes:
What are the disadvantages of multiple emitter-follower stages?
I'm thinking of say 3 or maybe even 4 EF stages, to obtain huge input impedance and 'voltage' input like a MOSFET stage. I realize that proper thermal compensation is needed and the higher Vbe (...wich doesn't go as high as Vgs of MOSFETS though).
What are the disadvantages of multiple emitter-follower stages?
I'm thinking of say 3 or maybe even 4 EF stages, to obtain huge input impedance and 'voltage' input like a MOSFET stage. I realize that proper thermal compensation is needed and the higher Vbe (...wich doesn't go as high as Vgs of MOSFETS though).
Internal resistor noise is not the concern. What else happens when the resistor values increase?
Hugh wrote:
Hugh wrote:
The transfer function of the feedback network is of the form Z1/(Z1 + Z2) where Z1 is the series combination of resistor and shunt capacitor. The capacitor is very much in the signal path.
Hi,Nrik said:
a three stage EF output with pre-driver, driver and output device is very common.
Read Leach's "low Tim" for a complete expose on designing his amplifier. It was invented back in the 1960s and still popular.
D.Self has majored on the two stage EF and again he has given us all the design details and more.
Four stage EF is unusual.
Everyone,
But, why not?
TB,
The maths is unmistakable but also shows that the influence of the shunt cap is considerably less than if it were in series with the signal passing to the fb node.
This was my point. I did not mean to imply otherwise, but my argument stands, and is confirmed subjectively over many years. A shunt cap acting on a signal has less sonic influence than one in series with the entire signal.
Hugh
The maths is unmistakable but also shows that the influence of the shunt cap is considerably less than if it were in series with the signal passing to the fb node.
This was my point. I did not mean to imply otherwise, but my argument stands, and is confirmed subjectively over many years. A shunt cap acting on a signal has less sonic influence than one in series with the entire signal.
Hugh
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