I also pointed an IR camera on the IPS board. As you can see Q5/Q6 are actually rather warm at 50°C. I hope this is not a long-term reliability issue. The hot spot below is R17 at 56°C. I also included a view of the entire board. Heat sink (3U 300mm) is at roughly 40°C (ambient is 20°C). Cold spots are not really cold spots, of course, but the effect of the low emmissivity on the shiny metal parts.
This is another improvement, for both the EF3-3 and EF3-4 boards, which lowers the already outstanding distortion numbers even further, and can be easily done while you guys are implementing the new bias spreader configuration. There were always a couple options for the feedback trace and routing to open the possibility of improvements either way, and this is not something that can be simulated but must be tested for confirmation. Which also has its challenges trying to measure distortion and minor changes accurately at such low levels.
In the process of testing the existing routing, it was decided to test a few more potential routes to see if there would be any improvement for future board revisions, or to decide on what feedback path would be best for the current PCB’s. A new route was found that in fact does improve the distortion performance and can be changed in a couple ways on the current EF3-3 and EF3-4 PCB’s.
There are two ways to go about this, depending on how you want to implement it. The existing feedback trace can be cut, and the solder mask scraped away, allowing the new solid core enameled wire to be soldered directly in place, or a simpler approach is to run a wire from the inductor to the IPS header, following the new path and existing trace. A low strand count wire helps here as it better holds its form. 20awg or 0.81mm wire is used in both cases.
In the process of testing the existing routing, it was decided to test a few more potential routes to see if there would be any improvement for future board revisions, or to decide on what feedback path would be best for the current PCB’s. A new route was found that in fact does improve the distortion performance and can be changed in a couple ways on the current EF3-3 and EF3-4 PCB’s.
There are two ways to go about this, depending on how you want to implement it. The existing feedback trace can be cut, and the solder mask scraped away, allowing the new solid core enameled wire to be soldered directly in place, or a simpler approach is to run a wire from the inductor to the IPS header, following the new path and existing trace. A low strand count wire helps here as it better holds its form. 20awg or 0.81mm wire is used in both cases.
EF3-3 Feedback Trace Mod
EF3-4 Feedback Trace Mod
The BDxx16S were chosen because of the binning consistency allowing for less variables in the design. We tested a few others, but they were either harder to obtain, no longer available, or just simply did not work in circuit as intended.
We did a lot of testing directly relating to RCC to verify and tune the Sim for the correct value, looking for the least error across Q104 as we swept the rail voltages. Bias will change regardless when the rail voltages due to temperature. I'm not sure if you are asking about THD? If so there were no changes on my regular sweep test, but that is at 25V 8 ohms, so to be expected. I am sure though that there would be better results at lower outputs, but trying to get consistent and repeatable results sometimes is not easy when there are too many variables at play.
Those temperatures are nothing for parts rated at 125°C, and nothing to be concerned about. What size of resistor are you using for R17?
Brilliant work as always. I have a very minor, but hopefully helpful suggestion. Since there are already two versions of the boards out in the wild, and it seems likely a third upcoming; could the key people in the thread please agree to a consistent nomenclature and potentially board silkscreen designations to differentiate between the various iterations. As an example, I truly don't know what boards are 'current' now, and in the future, it may be even harder to discern. It will be much, much easier to reconcile against the schematics etc.
I've followed both threads from the beginning, and I take detailed notes / copy paste into my personal build notes... and the build guide is second to none (IMO), but this minor change (or something similar) would be greatly appreciated.
Thanks again to everyone!
If you look on the boards the board version number is clearly marked.
These numbers correspond to PCB Version number listed at the bottom of the schematic for the relevant section Wolverine IPS & Precision EF3.
For clarity I'll list them below.
1st Group buy pcb's
Schematic Version 4.0
Wolverine IPS, PCB Version V3.7
Precision EF3, PCB Version V3.9
2nd Group buy pcb'sSchematic Version 4.3
Wolverine IPS, PCB Version V3.8
Precision EF3, PCB Version V4.0
I did just notice that the schematics for the 1st Group buy boards uploaded to the Dropbox folderwere incorrectly labeled, so I have upload the correct files now.
Sorry for any confusion.
Please note that all the changes / tweaks that we have made can be applied to both the 1st and 2nd Group buy pcb's
^ That is fantastic. Thank you so much!
If in future posts, we can all refer to what you've noted above (and future versioning) vs. terms like "current" or "group buy" version I think it would be tremendously helpful, particularly at the pace this incredible team iterates.
If in future posts, we can all refer to what you've noted above (and future versioning) vs. terms like "current" or "group buy" version I think it would be tremendously helpful, particularly at the pace this incredible team iterates.
Good idea, I'll keep that in mind. 👍
I have a small request, should a PCB revision occur. Can you designate pin 1 of the transistors? Some are no problem when the outline is an asymmetrical shape, but the TO-126 transistors are symmetrical and I have managed to put most of them in backwards. That's on me, as I made an assumption that where one particular pin is labeled (all the pins labeled B) that that was pin 1, which is always the left pin with the part number facing up. That is not correct, of course, but the current situation forces one to consult the data sheet, since the vendor pinouts for the different parts was apparently done using the "shuffle" setting. 🙂
^ Since Pin 1 may differ in its use based on that random shuffle... I'd suggest labeling CBE, GDS or equivalent instead. Example - Pin 1 may be C or E ... which gets you in the same pot o' hot water, IMO.
My suggestion always consult the datasheet until you know them from memory 👍🏻
Agreed 100%, but... if you're going to label... labeling "pin 1" is less useful (IMHO). I measure each part before installing.
Also... some parts like a J113 (I think it was that I ran across) may have different pinouts from different manufacturers of the "same" part.
So... just labeling the functionality on the boards is what I've found most useful. I typically ignore all the silkscreen hints like the little curves etc. Example... BC550 vs. ZTX450 are pretty much interchangeable in one circuit I'm using, but their pinout is 'opposite'. The only thing that 'matters' is CBE.
Also... some parts like a J113 (I think it was that I ran across) may have different pinouts from different manufacturers of the "same" part.
So... just labeling the functionality on the boards is what I've found most useful. I typically ignore all the silkscreen hints like the little curves etc. Example... BC550 vs. ZTX450 are pretty much interchangeable in one circuit I'm using, but their pinout is 'opposite'. The only thing that 'matters' is CBE.
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All the transistors are labeled BCE, etc on the silkscreen on the underside of the boards and all the bases are labeled on the top silk screen.
I usually make my pin 1 a square pad, all others being round. An easy queue without cluttering the silkscreen unnecessarily.
The base pads of all the transistors except for the output transistors are a little different to the other pads. You will need to look closely though. I believe that the silkscreen labels and what we have done is clear. You should always use a component tester to verify each transistor before it's installed. It just a good habit to get into. 🙂
I need some help from you folks. I am working on bringing up an EF3-3 board. I am at the point where J103 is installed and none of the output transistors. Other than that the build is complete.
During testing, I noticed a 6dB/oct roll off starting at 10kHz. I figured it was a cap off by 10 somewhere, but further investigation showed that the problem is actually slew rate limiting. I have swapped the IPS into a working EF3-4 with all of the output transistors, and in that rig, the whole amp works fine out to full power at 100 kHz. (Guys, best to heed the warning about full power testing above 20kHz, lest the magic smoke be released from the Zobel resistor.)
On the output stage I am bringing up, the output looks fine and flat at low amplitudes, and at full 96V pp at 1 kHz. However at full output swing, by 3 kHz distortion starts to set in, and by 4 kHz the output turns into a diminished triangle that gets smaller as the frequency rises. As soon as noticeable distortion shows on the scope, the two LEDs across the VAS get much brighter. I have tried varying the bias from min to max, and it makes a very slight difference in where the limiting starts, but there is no setting that seems to work correctly. Both rising and falling edges are affected, nearly identically. The swing is within 5 volts of each rail, perhaps a bit less on the negative side, but not more than 300 mV. Clipping seems to set in more or less symmetrically.
During testing, I noticed a 6dB/oct roll off starting at 10kHz. I figured it was a cap off by 10 somewhere, but further investigation showed that the problem is actually slew rate limiting. I have swapped the IPS into a working EF3-4 with all of the output transistors, and in that rig, the whole amp works fine out to full power at 100 kHz. (Guys, best to heed the warning about full power testing above 20kHz, lest the magic smoke be released from the Zobel resistor.)
On the output stage I am bringing up, the output looks fine and flat at low amplitudes, and at full 96V pp at 1 kHz. However at full output swing, by 3 kHz distortion starts to set in, and by 4 kHz the output turns into a diminished triangle that gets smaller as the frequency rises. As soon as noticeable distortion shows on the scope, the two LEDs across the VAS get much brighter. I have tried varying the bias from min to max, and it makes a very slight difference in where the limiting starts, but there is no setting that seems to work correctly. Both rising and falling edges are affected, nearly identically. The swing is within 5 volts of each rail, perhaps a bit less on the negative side, but not more than 300 mV. Clipping seems to set in more or less symmetrically.