Cascoding has a variety of benefits, among them simplifying models a bit.
One thing not often noticed: the input Z of the cascoding part is finite. Even when it is a bootstrapped cascode, the reduction of Miller C is limited by this, and the load in the upper device is significant in determining this Z.
One thing not often noticed: the input Z of the cascoding part is finite. Even when it is a bootstrapped cascode, the reduction of Miller C is limited by this, and the load in the upper device is significant in determining this Z.
With differential input pairs - cascoding with bipolars seem to have advantages over jfets. In the past, I have found simple neutralizing techniques do similar work to reduce (cancel) C. And, you can cancel completely the Miller C by added input c with series R to get same value. Little used techniques that dont cost much but are very circuit specific. Anyone tried these other methods? Comments, pls. -Thx RNM
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Bipolars at the same current will always trump JFETs or DMOS parts, unless the latter are huge. This is true in particular if there is a lot of voltage swing/gain at the upper collector. An intriguing question: under what conditions is a given part or set of paralleled parts optimal for reducing the overall input capacitance of the cascoded stage? I.e., how huge is huge?
This isn't offered rhetorically btw.
With some input series R to work with -- maybe similar value to stage load R --- the effective output C formed by the stage gain when matched with input C, will cancel. that is add more input c to equal the gain stage output C. The input and output being of opposite phase will cause any signal thru the C's to cancel.... thus making the C seem to not be there or zero equivalent. No cascoding needed and distortion from this source is reduced. [if you can have more input C for your appl]. Just a point of conversation. ideas.
For people's information, I just tried the model of the BF862 that's being used in LTspice, and it does add a gentle curve, slope decreasing towards zero gate voltage, to the transconductance characteristic; a simple, minimal spec'd set of parameters for a JFET just traces a straight line, otherwise.
Frank
Frank
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Circuitmaker Pro something. No longer supported afaik, and I have devised many patches around its bugs.
I've been meaning to download LTSpice. It seems to be becoming something of a de facto standard.
I'm not sure you gain much from this.
The two major distortion mechanisms of 'Miller' capacitance are
- degraded PSR cos the PS directly modulates the VAS (and also a none cascode LTP) via the 'Miller' capacitor. Often appears as THD unless your PSU is as complex as the amp.
- Cob is highly non-linear cos it depends on Vcb
The improvements I've managed on FET990 are mainly by dealing with these 2 issues which I can confirm are very real from my misspent youth.
I'm rather impressed that LTspice seems to sim these quite nicely.
Any FET guru care to pontificate on the above as my real life experience with the above is all with BJTs?
Your experience is exactly the same as mine. In fact, I could fine tune the cancellation to a null-once I was close - by adjusting the supply voltage. So, yes, a stable ps voltage is required. Its a first order cancellation that for a high gain input stage could open its bandwidth and help lower thd at the high end for gnfb circuits. Just something off beat for the sim guys here.
In regards to cascoding, as used here.... of all the combo's of fet/bipolar, fet/fet or bipolar/fet, bipol/bipolar -- the fet with bipolar cascode does the better job. Comments? Thx - RNM
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things for the sim guys
You should be able to see this cancellation affect in sim if your models are really good.
Another to see how the sim does is with neutralization.... an old trick is to put back biased diodes -- made from the same devices as the diff pair -- from base to opposite collector. This has the added benefit of varying the c with signal voltage for better results. Can compare to cascode
[In either case, reducing the effective C not only extends Bw but by reducing the range of C variation with voltage, some distortion reduction can be seen.]
Something for the sim guys... may have appl in other designs they make.
You should be able to see this cancellation affect in sim if your models are really good.
Another to see how the sim does is with neutralization.... an old trick is to put back biased diodes -- made from the same devices as the diff pair -- from base to opposite collector. This has the added benefit of varying the c with signal voltage for better results. Can compare to cascode
[In either case, reducing the effective C not only extends Bw but by reducing the range of C variation with voltage, some distortion reduction can be seen.]
Something for the sim guys... may have appl in other designs they make.
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The way the cascode is made might be more important than what semis are used. Attached is a cascode evaluation made by Stinius.
/S
/S
It only works if the inputs are symmetrical which is not the case with the common input LTPs, thus it will degrade performance.
This affect can indeed be seen with sim when the above criteria is met.
What about the effects of cascoding on PSRR ? Who showed the best topology for those parameters?
When designs are not mainly focused on lowest distortion, I find that the improvment to PSR to make an audible different in power amps with unreg supplies. I have cascoded compl/diff input designs with already very low thd and found audible improvement.... I attributed it to improved psrr. Thx-RNM
When designs are not mainly focused on lowest distortion, I find that the improvment to PSR to make an audible different in power amps with unreg supplies. I have cascoded compl/diff input designs with already very low thd and found audible improvement.... I attributed it to improved psrr. Thx-RNM
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SPICE 3 includes a fitting parameter B from the Parker and Skellern model, but all the JFET's I see just use the same default value. I don't know if this is enough since I found several articles that needed to modify their model to fit distortion performance of real amplifiers. Time to get out the BF862 datasheet and experiment.
Attachments
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That helps in any case, but it would be fun if a simulation could catch the load line tweaks.
jfets as cascode devices has an impedance advantage over bipolars... so while capacitance is lower with bipolar the impedance is also lower, so the current swing over rail resistors add more distortion due to waring drive current. each type has their over benefits in cascoding