Hi, @diyiggy and all folks 🙂
I can propose one +5V, still simple, Shunt_End module. 😎 With improvement over the standard configuration.
Just 2 small BJT, and 2 passive elements added... In this example 40mA is consumption and shunt is about 120% of total consumption. The rato could be changed. Internal resistance of the end capacitor is the factor and should be low as it can be. I optimize all parts, current limiter, current source in current limiter, put 6mA to tl431. I think this is the optimal. very good behaviour, with not so much elements? (Transitor types offcourse could be different. I put theese because they are available.)
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Tomorrow I will sketch for each PS section...
Cheers
I can propose one +5V, still simple, Shunt_End module. 😎 With improvement over the standard configuration.
Just 2 small BJT, and 2 passive elements added... In this example 40mA is consumption and shunt is about 120% of total consumption. The rato could be changed. Internal resistance of the end capacitor is the factor and should be low as it can be. I optimize all parts, current limiter, current source in current limiter, put 6mA to tl431. I think this is the optimal. very good behaviour, with not so much elements? (Transitor types offcourse could be different. I put theese because they are available.)
.
Tomorrow I will sketch for each PS section...
Cheers
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Ok, remember, my notes cover what I will build with "whatever is Lion around"...
Here is what I intend to do for the main power supply for the TDA1541 and analogue stages:
My main element of the power supplies are Supercapacitors, Elna Dynacap DU series, each is rated 25F/2.7V and in practice measures 10mOhm ESR.
There are ultimately 32pcs for TDA1541 & analogue stages, or 6,250,000uF @ 40mOhm for the TDA1541 and 3,125,000uF @ 80mOhm for each audio output.
The TDA1541 section of the circuit use an 8S2P setup of these capacitors. Using a bunch of TL431 set to 2.5V and connected directly across the capacitors makes sure voltage sharing and regulates DC.
Each TL431 is ~0.15 Ohm and 20uV random noise. Each Supercapacitor Block is 50F/5mOhm. So the 20uV noise is passively squashed to 0.67uV with a turnover at 20mHz.
If we connect 8 such sections in series, we get the usual rootsumsquare adding, so 8 sections give not 8 times higher noise, but only 2.828 times, so less then 2uV between +5V and -15V.
The negative supply (aka DGND) for the EC Logic is tapped off from the main circuit with an inductor and 4pcs 1,200uF Os-Con, to make a well isolated Logic supply for the logic frontend. Generally speaking there should be little to no logic noise on DGND (see my previous posts for more details).
The analogue output section will use 8S1P with 10K resistors (not shown) across each capacitor to force voltage sharing. It is isolated from the TL431 Noise by 6 ohm + 6mH lowering noise even further. This gives another 37dB passive noise attenuation at 1Hz and more above. This is important as my planned output stage has ZERO PSRR!
Some people may scoff at the LM317 CCS and AC CCS/ DC Regulator, but it provides a high impedance between near DC and up to 10kHz (~600kOhm based on what Walt Jung measured)...
The idea behind using three Schottky diodes in series (which will cause headscratching and derision) is to reduce the coupling capacitance. Using 1N5817 should be fine (3 X 20V = 60V) but 1N5818/19 have lower capacitance, so let's use 1N5819 and with reduces the nominal 110pF reverse capacitance to 37pF. I happen to have many SR2100 (2A/100V) and will use these instead. Anyways, reducing capacitance in turn raises the resonance frequency with the mains transformer, allowing the snubber across the secondary (not shown) to use much less large parts.
The "inrush current limiter" NTC's are used as dynamic resistors. The idea is simple. When the super capacitors get charged we want maximum possible current to charge as fast as possible.
There is a circuit that senses "Voltage at 90%" around TL431 U1 and actuates a relay that enables R2 to drop the charge current to 0.2A instead of (in theory) 0.833A (and signals "TDA1541 Ready" to the control logic). Looks ~5 Minutes "pre-charge" time for the power supply. Without speedup measures "pre-charge" time looks more like 60 minutes, not something I find acceptable.
The Thermistors start at 10 Ohm each (seriously limiting instant current into the supercapacitors and other parts of the circuit) but rapidly heat up and loose resistance, down to below 1 Ohm. As the current drops, because our capacitors become charged the thermistors cool and the resistance rises again, somewhat below 10 Ohm but much greater than 1 Ohm.
Bigger input resistance causes a wider, lower peak current current draw from the transformer and better damping of resonances. Here it looks like we get 0.65A peak with nearly 90 degrees conduction and around 300mA RMS.
With a short instead we are looking at 1A peaks with 45 degree conduction and 400mA RMS current and more output voltage .
The RC ladder in the PSU already drops the ripple to below 1mV peak-peak with a nice sinewave shape. before we get into any electronics.
It's of course all heavy duty overkill, but ask the 96's Strategic Airwing from SAC if they ever received complaints from anyone "overkilled" during the Arc Light missions they used to fly with their B-52's from U-Tapao Base right across the gulf of Siam from me.
I doubt it, nobody ever complained about being overkilled. Not even noise.
Thor
Here is what I intend to do for the main power supply for the TDA1541 and analogue stages:
My main element of the power supplies are Supercapacitors, Elna Dynacap DU series, each is rated 25F/2.7V and in practice measures 10mOhm ESR.
There are ultimately 32pcs for TDA1541 & analogue stages, or 6,250,000uF @ 40mOhm for the TDA1541 and 3,125,000uF @ 80mOhm for each audio output.
The TDA1541 section of the circuit use an 8S2P setup of these capacitors. Using a bunch of TL431 set to 2.5V and connected directly across the capacitors makes sure voltage sharing and regulates DC.
Each TL431 is ~0.15 Ohm and 20uV random noise. Each Supercapacitor Block is 50F/5mOhm. So the 20uV noise is passively squashed to 0.67uV with a turnover at 20mHz.
If we connect 8 such sections in series, we get the usual rootsumsquare adding, so 8 sections give not 8 times higher noise, but only 2.828 times, so less then 2uV between +5V and -15V.
The negative supply (aka DGND) for the EC Logic is tapped off from the main circuit with an inductor and 4pcs 1,200uF Os-Con, to make a well isolated Logic supply for the logic frontend. Generally speaking there should be little to no logic noise on DGND (see my previous posts for more details).
The analogue output section will use 8S1P with 10K resistors (not shown) across each capacitor to force voltage sharing. It is isolated from the TL431 Noise by 6 ohm + 6mH lowering noise even further. This gives another 37dB passive noise attenuation at 1Hz and more above. This is important as my planned output stage has ZERO PSRR!
Some people may scoff at the LM317 CCS and AC CCS/ DC Regulator, but it provides a high impedance between near DC and up to 10kHz (~600kOhm based on what Walt Jung measured)...
The idea behind using three Schottky diodes in series (which will cause headscratching and derision) is to reduce the coupling capacitance. Using 1N5817 should be fine (3 X 20V = 60V) but 1N5818/19 have lower capacitance, so let's use 1N5819 and with reduces the nominal 110pF reverse capacitance to 37pF. I happen to have many SR2100 (2A/100V) and will use these instead. Anyways, reducing capacitance in turn raises the resonance frequency with the mains transformer, allowing the snubber across the secondary (not shown) to use much less large parts.
The "inrush current limiter" NTC's are used as dynamic resistors. The idea is simple. When the super capacitors get charged we want maximum possible current to charge as fast as possible.
There is a circuit that senses "Voltage at 90%" around TL431 U1 and actuates a relay that enables R2 to drop the charge current to 0.2A instead of (in theory) 0.833A (and signals "TDA1541 Ready" to the control logic). Looks ~5 Minutes "pre-charge" time for the power supply. Without speedup measures "pre-charge" time looks more like 60 minutes, not something I find acceptable.
The Thermistors start at 10 Ohm each (seriously limiting instant current into the supercapacitors and other parts of the circuit) but rapidly heat up and loose resistance, down to below 1 Ohm. As the current drops, because our capacitors become charged the thermistors cool and the resistance rises again, somewhat below 10 Ohm but much greater than 1 Ohm.
Bigger input resistance causes a wider, lower peak current current draw from the transformer and better damping of resonances. Here it looks like we get 0.65A peak with nearly 90 degrees conduction and around 300mA RMS.
With a short instead we are looking at 1A peaks with 45 degree conduction and 400mA RMS current and more output voltage .
The RC ladder in the PSU already drops the ripple to below 1mV peak-peak with a nice sinewave shape. before we get into any electronics.
It's of course all heavy duty overkill, but ask the 96's Strategic Airwing from SAC if they ever received complaints from anyone "overkilled" during the Arc Light missions they used to fly with their B-52's from U-Tapao Base right across the gulf of Siam from me.
I doubt it, nobody ever complained about being overkilled. Not even noise.
Thor
For those interested, my small contribution to the DIY community.
There are three files
1) Vertical PCB with the CPLD on board
2) Horizontal PCB SAA7220 to CPLD adapter
3) Horizontal PCB from TDA1541 i2s to TDA1541 PCM
All this greatly facilitates the possibility of switching from one mode to another with simple extractions and insertions obviously later with the use of sockets.
Hi there is one version of power supply i did last few days. Al of the main modules i used before.
Power supply consists of 3 main parts (after the transformer). One passive LC filter - Pre-Regulator - Shunt end regulator.
The shunt regulator is good to be on same PCB as DAC chip because of shorter connection.
All discrete circuit, with available parts. Most parts are from same era as the DAC chip 🙂 . Except very low ESR capacitors.
But this PS is using moderate or lower capacitor values.
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PS has very good filtration and very low output resistance. I simulated for standard and for max consumption and with IV section consumption too. I tried to achieve good thermal values, without unnecessary dissipation.
Also used a more realistic L models, and put in the ESR of Cs. (I didn't put the shot-key diodes because I cant find them in the libs...)
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Maybe the Shunt can be "off" DAC PCB, but with very short connections?
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I am posting separatley Pre-Regulator and Shunt, I forgot to capture PDF of merged... Sorry
Power supply consists of 3 main parts (after the transformer). One passive LC filter - Pre-Regulator - Shunt end regulator.
- Passive filter is classic and simple.
- Pre-regulator is also classic, non feedback, darlington pass transistor, no high values of C...
- Shunt-end.reg might look as "complicated" but in essence it is simple with repeating sections.
The shunt regulator is good to be on same PCB as DAC chip because of shorter connection.
All discrete circuit, with available parts. Most parts are from same era as the DAC chip 🙂 . Except very low ESR capacitors.
But this PS is using moderate or lower capacitor values.
.
PS has very good filtration and very low output resistance. I simulated for standard and for max consumption and with IV section consumption too. I tried to achieve good thermal values, without unnecessary dissipation.
Also used a more realistic L models, and put in the ESR of Cs. (I didn't put the shot-key diodes because I cant find them in the libs...)
.
Maybe the Shunt can be "off" DAC PCB, but with very short connections?
.
I am posting separatley Pre-Regulator and Shunt, I forgot to capture PDF of merged... Sorry
I have only combined -db graph of pre-reg + shunt with decoupling. I will post tomorrow sorry.
red=+5V, green=-5V, blue=-18V, yellow=DGND. With typical DAC consumptions + 10mA for IV.
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red=+5V, green=-5V, blue=-18V, yellow=DGND. With typical DAC consumptions + 10mA for IV.
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Isn't it a mistake that C4 is not parallel to R4? The datasheet suggests connecting Cadj from the ref input to the ground.
Nope, it's international.
Look at the lower 317 connected as CCS.
Then redraw the top one strictly in AC terms.
You will see for AC it's a CCS, with high output impedance, which is intentional
Thor
A comment or two, if you add an inductor with 0.1R DCR after the shunt, there is little point of lowering output impedance. Add a boost transistor if more current is needed. All else doesn't really help.
Alternatively, split the jobs.
Use the TL431 for DC precision and the 3-Transistor compound for AC behaviour.
Use a 2N4403 as input transistor for lowest noise, MPSA18 as VAS and BD13X (or one of the Japanese TO-220 full pack driver transistors for audio amplifiers) as output transistor.
Use a feedback capacitor (~100uF) from 431 Cathode to ADJ to make it a DC only shunt. It still has 20uV noise and 0.15 Ohm typical Zout.
So put an RC between the Cathode and the 3-Transistor compound to filter this noise. Say 1k/1000uF (to the rail being regulated) giving an 0.16Hz turnover.
So -40dB @ 16Hz and thus << 0.2uV noise at the input to the 3-Transistor Compound and also 0.16Hz as corner for the active regulation.
A 3-Transistor compound should get into single digit mOhm impedance to well beyond 20kHz. So this power supply can directly supply TDA1541 with minimal impedance, noise and distortion for any AC currents being sunk by the AC shunt.
Pre-regulator seems overkill.
A few suggestions:
Use two to four diodes in series to reduce diode capacitance. Use the lowest current Diodes that will do, they will have the lowest capacitance.
Place a snubber with R ~ Transformer ESR (primary DCR divided by ratio + secondary DCR) and C ~ 0.1...1uF across the transformer winding.
Place NTC and/or Resistors before/between capacitors. You may find you can scratch the regulator afterwards.
Your open loop pre-regulators show 2 X VBE drift, fold the Darlington up with an opposite polarity driver transistor and both thermal; drift and VBE offset essentially disappear.
Finally, why 2 X TL431 shunt in the -5...-15V branch? Use one with 1K1 & 3k3.
Thor
I am not trying to do THAT snubber. NO parallel capacitor (pointless).
It is less of a guesstimate (optimum R is always = ESR) and more overkill (way too large capacitor).
Thor
Yes. I put the serial Rdc of the L later in the PDF as 0.002 ohm. From the datasheet of some Bobbin inductor.
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OK. I think that to220 is better for high current BJT as efficiant heat distribution. I used before TIP31 / 32.
Do You mean the D44H11 (NPN) and the D45H11 (PNP)?
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I think that I tried it but the noise is higher. I will check it again. Thanks.
,
OK. Thanks.
Yes. I tried some values in RC net after the double L on core, but without significant success to correct this dip after the LC filter...
(For the transformer I think I have in neighbourhood a measurement device that can determine correct values for RC snubber.I consider this but didnt put on the sch 🙁 Also Jim Hagerman have an good article about it at http://www.hagtech.com/pdf/snubber.pdf)
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OK. Which type You can suggest to use?
Thanks.
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Probably You refering to 1st 2 caps after the rectification?
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It is not clear to me - could You please make some skatch?
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Yes. But anyway we need cascaded serial power shunt BJTs for make equal distribution of dissipation. And make the heatsinks all from same dimensions?
the trade off aftermath is few small bjt-s only?
And we have additional -10V supply eventually for direct coupling tube stage vith smaller -Ug @ Riv. More tubes available...
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I was thinking in the way of testing the complete power supply without the load. When all currents going troug the shunt power BJTs. In that case the disipation is maximal, and heatsinks should stand it just warm. And to match the heat on pass transistors and shunt one as within smaller range again to use same heatsinks...
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The key point is to adoopt -5V sufficient consumption shunt current when the load is present. Because on this shunt BJT current is smallest one.
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Also I think that L between AGND and DGND has to be as high as possible and low Rdc as possible. With opposite parallel diodes...
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Thanks for all of Your inputs they are very useful to me.
cheers.
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1.5mH with 2mOhm DCR!!!????
Do they wind it with a supraconductor?
The inductors I use (Panasonic) are TH, near the largest commercial bobbin and are 1.5mH, 600mA, 1.5R DCR.
No. Japanese transistors designed for Audio commonly have higher FT and Beta than about anything US/EU except real BD13X. An example in TO-126 is the 2SB649AD, with a beta > 160 and 140MHz Ft at 100mA and 2SA1306Y in TO220FP with beta > 120 and 100MHz Ft at 100mA. Many others (and better I think) exist.
This is NOT the point. The point is to make the TL431 only do DC.
The bit you ignored is the crucial part in this to make it work.
Base of input transistor of triplet compound (which is inverting) to supply rain (1,000uF). 1k between Base of input transistor of triplet compound and TL431.
Now the TL431 ONLY does DC not AC.
The Triplet is biased for the DC operation by TL431, in terms of noise, AC impedance etc. the triplet is the sole determining element.
You do not know folded 2-transistor emitter follower?
The concept of "correct value" actually means "correct according to a specific set of goals".
How do you know the goals are correct?
Did you look at and read the details I gave for my own projects Supercapacitor based PSU?
1N5819 for example.
Did you look at and read the details I gave for my own projects Supercapacitor based PSU? It shows precisely what I mean.
Why do we need equal distribution of dissipation?
And even if for some strange reason we do, given that each supply draws different currents your approach doesn't work anyway, -15V > -5V Shunt always has more dissipation. Design for it (bigger heatsink).
Thor
Ok, homestretch on designing circuits...
This time the analogue stage.
Input -4mA P-P current with -2mA DC current offset
Output ~2V RMS from 120R source impedance SE
~4V RMS from 240R source impedance BAL
To explain this let me introduce to not really a "new" circuit but rather a DJ Remix/Mashup featuring Baxandall Super Pair and Sziklai Compound feedback pair.
Meet the SziXandall Super Triplet (SXST):
Shown here is the "N-Channel" Version.
Compared to conventional bipolar circuits it offers multiple benefits for linear AC application:
1) There is no conventional Vbe (it is close to Zero, inherited from the Baxandall Super pair) and no appreciable thermal drift if T1/T3 are closely coupled
2) The Beta and thus the input impedance is extremely high, comparable to a darlington pair, if using BC560C & MPSA18 we are looking at a beta of appx 500,000 for AC input, again, this is inhereted from the Baxandall Super Pair.
3) The transconductance is very high. It is still emitter current dependent, but high. A Baxandall pair with a total of 3.5mA working current would produce around 130mA/V, with MPSA18 & BC560C SXST and ~0.25mA in the NPN and 3.25mA in the final PNP we get ~5,000mA/V transconductance (these numbers are rough estimates).
In most cases the SXST can replace classic Sziklai Pairs, Darlington Pairs, Super pairs, single transistors and Mosfets with highly predictable, highly linear construct made from extremely generic bipolar transistors. SMT dual NPN/PNP transistors that are BC5X0C equivalent exist from multiple vendors, using these ensures good parameter match and thermal coupling.
The Analogue stage uses this circuit in a "P-Channel" as a current conveyor from Aol/Aor to the negative TDA1541 rail (-15V) and a "pullup" CCS to +5V. This current conveyor keeps the TDA1541 at 0V with a very low thermal drift, very low input impedance and thus AC voltage on the TDA1541 output, offering near "ideal" operating conditions.
The available voltage overhead from the negative rail allows full 2V RMS to developed across a resistor acting as current to voltage convertor. With a Beta of ~500,000 and reduced current modulation in T1 due to the Sziklai pair action, the base current modulation - the only circuit node other than the CCS where AC current can "escape" is minimal and way below 1/2LSB. The collector impedance of our CCS is appx. 10MOhm compared to a few ohm input impedance of the current conveyor, so again any "current escape" is a small fraction of 1/2 LSB.
Thus it is fair to state that entire signal current from our TDA1541 passes through the 1.5kOhm and develops a voltage that is directly proportionate to the TDA1541 current. Our active circuit essentially disappears. Something similar may be done using a P-Channel Mosfet, if something suitable can be found, but accurate models are needed, with these no currently readily available options were convincing.
Following the I/U conversion resistor is a Buffer/Splitter that allows SE or balanced output and includes a Sallen-Key lowpass filter that is either peaking to equalise the NOS SINC roll-off at CD standard sample rates or an appx. 60kHz lowpass with an appx. 50dB/decade (~2.5 order) slope between 80khz & 800kHz and a final 4th order slope. The frequency response shown is the SINC compensation, nothing to see for the normal lowpass.
Why not (delete as appropriate) Tubes / JFET's / Depletion Mosfets / Enhancement Mosfets / Germanium Transistors / GANFET's / transformers / other? Well, most of these are difficult to procure out here in the boondocks and generally I could not see benefits from these in a sim.
BJT's have very consistent threshold voltages and thermals, the way J-Fet's and MOS-Fet's lack. Making do with a total of 20V Supply for 4V RMS Signal (11.2V PP) means we cannot afford unpredictable thermals, need to be able to reliably compensate thermals and cannot afford large threshold voltages.
Feel free to use whatever you like. It is for example totally possible to follow the I/U conversion resistor with a cathode follower, couple it capacitively to a 1:1 Transformer etc. et al. If 1.5kOhm output impedance are not a dealbreaker, we can even just use a coupling capacitor directly out from the resistor, done.
The Power supply for the output buffer is 8 X 25F/2.7V per channel, giving ~3,000,000uF with 80mOhm ESR and 20V DC the one for the TDA1541 and Current Conveyor are also covered in that post.
Home stretch, last bits of circuitry will cover the inputs and DEM reclock.
Thor
PS, a lot of sim time was spend on start-up, stability and resilience of the circuit to various transistor (spice models), but minor adjustment may be needed for stability, DC operating points and/or lowest HD.
This time the analogue stage.
Input -4mA P-P current with -2mA DC current offset
Output ~2V RMS from 120R source impedance SE
~4V RMS from 240R source impedance BAL
To explain this let me introduce to not really a "new" circuit but rather a DJ Remix/Mashup featuring Baxandall Super Pair and Sziklai Compound feedback pair.
Meet the SziXandall Super Triplet (SXST):
Shown here is the "N-Channel" Version.
Compared to conventional bipolar circuits it offers multiple benefits for linear AC application:
1) There is no conventional Vbe (it is close to Zero, inherited from the Baxandall Super pair) and no appreciable thermal drift if T1/T3 are closely coupled
2) The Beta and thus the input impedance is extremely high, comparable to a darlington pair, if using BC560C & MPSA18 we are looking at a beta of appx 500,000 for AC input, again, this is inhereted from the Baxandall Super Pair.
3) The transconductance is very high. It is still emitter current dependent, but high. A Baxandall pair with a total of 3.5mA working current would produce around 130mA/V, with MPSA18 & BC560C SXST and ~0.25mA in the NPN and 3.25mA in the final PNP we get ~5,000mA/V transconductance (these numbers are rough estimates).
In most cases the SXST can replace classic Sziklai Pairs, Darlington Pairs, Super pairs, single transistors and Mosfets with highly predictable, highly linear construct made from extremely generic bipolar transistors. SMT dual NPN/PNP transistors that are BC5X0C equivalent exist from multiple vendors, using these ensures good parameter match and thermal coupling.
The Analogue stage uses this circuit in a "P-Channel" as a current conveyor from Aol/Aor to the negative TDA1541 rail (-15V) and a "pullup" CCS to +5V. This current conveyor keeps the TDA1541 at 0V with a very low thermal drift, very low input impedance and thus AC voltage on the TDA1541 output, offering near "ideal" operating conditions.
The available voltage overhead from the negative rail allows full 2V RMS to developed across a resistor acting as current to voltage convertor. With a Beta of ~500,000 and reduced current modulation in T1 due to the Sziklai pair action, the base current modulation - the only circuit node other than the CCS where AC current can "escape" is minimal and way below 1/2LSB. The collector impedance of our CCS is appx. 10MOhm compared to a few ohm input impedance of the current conveyor, so again any "current escape" is a small fraction of 1/2 LSB.
Thus it is fair to state that entire signal current from our TDA1541 passes through the 1.5kOhm and develops a voltage that is directly proportionate to the TDA1541 current. Our active circuit essentially disappears. Something similar may be done using a P-Channel Mosfet, if something suitable can be found, but accurate models are needed, with these no currently readily available options were convincing.
Following the I/U conversion resistor is a Buffer/Splitter that allows SE or balanced output and includes a Sallen-Key lowpass filter that is either peaking to equalise the NOS SINC roll-off at CD standard sample rates or an appx. 60kHz lowpass with an appx. 50dB/decade (~2.5 order) slope between 80khz & 800kHz and a final 4th order slope. The frequency response shown is the SINC compensation, nothing to see for the normal lowpass.
Why not (delete as appropriate) Tubes / JFET's / Depletion Mosfets / Enhancement Mosfets / Germanium Transistors / GANFET's / transformers / other? Well, most of these are difficult to procure out here in the boondocks and generally I could not see benefits from these in a sim.
BJT's have very consistent threshold voltages and thermals, the way J-Fet's and MOS-Fet's lack. Making do with a total of 20V Supply for 4V RMS Signal (11.2V PP) means we cannot afford unpredictable thermals, need to be able to reliably compensate thermals and cannot afford large threshold voltages.
Feel free to use whatever you like. It is for example totally possible to follow the I/U conversion resistor with a cathode follower, couple it capacitively to a 1:1 Transformer etc. et al. If 1.5kOhm output impedance are not a dealbreaker, we can even just use a coupling capacitor directly out from the resistor, done.
The Power supply for the output buffer is 8 X 25F/2.7V per channel, giving ~3,000,000uF with 80mOhm ESR and 20V DC the one for the TDA1541 and Current Conveyor are also covered in that post.
Home stretch, last bits of circuitry will cover the inputs and DEM reclock.
Thor
PS, a lot of sim time was spend on start-up, stability and resilience of the circuit to various transistor (spice models), but minor adjustment may be needed for stability, DC operating points and/or lowest HD.
I will use the Chinese CPLD IIS 2 SIM board.
To quote a famous artists who put a used toilet on show at a Museum: "It's a ready made!"
It states it uses FIFO output mode of the CPLD, which I checked and such exists, I guess we need to take it "on faith".
Each macro cell terminates into a latch and the clock routing seems ok.
TBH, I'd probably still prefer discrete logic, with all the extra control it offers over all that FPGA/CPLD stuff, as I am notoriously short on faith, long on suspicion and prefer to carry a big gun.
I guess I'm the kinda guy, who, in hell will be in good company.
Given the above, the outputs then should be low enough jitter as the CPLD uses MCK for re-clocking. The CPLD is described by the CPLD vendor as targeted at clocking applications.
For 16 Bit / 44.1kHz which is what most of us listen to most of the time, 1/2 LSB is equivalent to 173pS. One hopes that LE is less. Some literature suggests 120pS (+/-60pS) Peak-Peak additive jitter for these CPLD devices, but it still depends on coding.
Obviously a lot trust to place into Chinese CPLD code, but as long as we try to use DIY Friendly logic (e.g. TH) and reliable (meta stability, set-up time etc.) re-clocking from a 45/49MHz MCK we are a bit up sh!tcreek, possible with a minor surfeit of a boat and paddle. So let me give it up as a bad job.
Best I can find is "F" series which according to John (ECD) Brown adds 26ps jitter per latch, so two in series to eliminate meta stability a minimum of 52pS jitter added. PECL is available in TH packages, but not that easily sourced either and a lot of extra parts are needed to make best use of it.
The Chinese CPLD PCB has output R & C on board, which I will change to what is needed for the slew rate limiter.
I will add the clipping diodes below the main PCB (actually Veroboard) on the pin's used for a single TDA1541 (rest RC on unused outputs removed) with a single bias circuit for all diode clippers:
Using diode clipping over simple RC attenuation means we get a more predictable and "clean" waveform. If this is material remains a question. But in terms of "electronic æsthetics" a clock or data pulse that looks like a perfect truncated pyramid seems more interesting and more likely to trigger repeatedly perfectly than a severely rounded square wave. Clearheaded analysis tells us - no it ain't matter, who knows.
The Bias circuit is basically a self biasing Baxandall Super pair used as follower. It's reference voltage is generated from two diode connected transistors (all diodes inside the TDA1541 are actually diode connected transistors) intended to be placed below the TDA1541, to track the temperature closely.
As the circuit always "pulls down" current from the 1.65V centre of 3.3V CMOS logic, a PNP output version was selected. The current mirror sets the output bias at the same current (+/- common errors) eliminating thermal and DC error if the transistors are well matched. Even with normal mismatches offsets are a few mV. As set the 620R sets around 1mA in each transistor.
The rest here is the DEM clocking. As we need to use RF style DEM and supply decoupling anyway, to control the DEM matrix switching glitches at Fdem which are ~ 10....20nS wide (you need a really fast 'scope to see them) plus seeing that in practice the "very low frequency" DEM operation seems to impact linearity after all and needs compensation circuits and adjustment (that I expect needs adjusting with seasons and aging) the choice seems obvious.
I decided to retain the DEM circuit as designed to run at high frequencies, with high quality film and ceramic type decoupling capacitors sized suitably. Like everything, it is a compromise and I now have bags full of Nichicon KL Capacitors already bought to spare.
Correct supply routing and decoupling as well as correct sizing and routing of DEM filter capacitors should reduce the problems caused by the current ripple and switching glitches in the common "dump everything to AGND" layouts dramatically.
DEM re-clock simply uses 74F74 in PDIP14. The intended "74F" logic is non-saturating bipolar, not CMOS. So we have a lot of DC current draw and current modulation with logic state (not a lot), but not the very high speed current spikes each time a CMOS inverter switches (remember any CMOS Circuit is many inverters in series). Plus 74F is much faster than HCMOS (125MHz typical maximum clock) - mostly the only other "fast" game in town in PDIP.
It would be possible to use 74AC logic in PDIP as well, but AC logic has a well deserved reputation for being very bitchy, noisy and a nightmare, plus it's only marginally faster than 74F. So 74F it is.
A chain of two 74F74 IC's (four flip flops) divides the 64 X WCK BCK down by 16 and provides a differential drive at 64 X WCK / 16 = 4 X WCK. For less supply current and noise using an 74LS74 for the final two Flip Flop's may be a good choice, slow logic is not necessarily a bad thing. Note this under TBD.
This setup with 4 X WCK always uses the lowest DEM clock that fulfils the constraints I set out in my analysis of DEM frequency recommendations. In my view it is best to use the lowest DEM frequency that makes sense, as it keeps any problems to the minimum.
As alternative, we could use 4 X the highest sample rate (384kHz) and thus a 1.4112/1.536MHz fixed DEM frequency, but we now dramatically increase the frequency of our DEM Matrix switching glitches even at lower sample rates and unnecessarily so. It would be interesting to hear from those who have done a rigorous and structured comparison between 176.4kHz & 1.411MHz or even 2.822MHz and what their conclusion was.
This also can be easily done by dividing MCK instead of BCK and I may try it out anyway.
The main benefit I can see for 1.4/1.5MHz DEM is that we can reduce the DEM Filter capacitors a lot more. With only ~200n needed on MSB to match the 2uF I will add, an all C0G setup with low values becomes feasible. But as I have the ECPU film capacitors in hand anyway....
The coupling circuit to the TDA1541 oscillator goes back to Tubee and has been noted by a number of people as preferred to the 10K/2k2 divider shown by John, which I have used previously, though if needed the circuit is easily converted. I read it being called "the best"circuit multiple times in comparison to John's design.
The advantage of tubee's circuit is that no currents are injected into -15V whatsoever and the significantly attenuated signal forces the local oscillator into phase lock.
That's it. Time to start drilling the faux Goldmund Chassis from China, drill Veroboard's and start on making this a working DAC, not just an idea!
Thor
Since we don't need regulation but low noise, may be this configuration will suffice? Very low noise and impedance is about 90mOhm flat to the MHz region
I'll be making a pcb regarding these info. Supercaps are obsolete (elnas), but footprint should remain the same for replacement ones. I don't mind running the board a little bit larger, so hardware i²s to sim it is (critical part, seems unfair to leave it to chance in chinese cpld code, although i don't mind leaving a space for chinese addon board stack). I'm still down for chinese amanero as that one is trialed and tested in many multibit builds. And WM8804 is still up for grabs in sufficient quantities (waaaay less tda chips) so it will be on board for this project. One thing to note, since it's a group project, give suggestions for cases where you would like to fit this into, and most liked will be chosen as base dimensions.
We don't really need low noise, just low enough. And 3 X TL431 is low enough.
The worst supply noise rejection is on -15V and is 58dB. So the 20uV from the TL431 drops to ~28nV, good enough in my books.
What we need is low impedance from DC to ~100MHz!
That is a very marginal improvement on a plain TL431 if you ask me.
Thor
Others are at the same job, lets make a joint effort, not isolated, please everyone get in touch with each other and copy me into a group.
Thor
Hi guys, taking nothing away from the proven skill of @ThorstenL , whom I thank for his precious advice and his enormous amount of time made available to this thread, I would like to know any differences between the CPLD IIS 2 SIM board system proposed by Thor and the one proposed by me (my credit is only from the hardware point of view) ,alls credits for writing the VHDL code (open and free for all) , go to @miro1360 .
https://electrodac.blogspot.com/p/i2s-to-pcm-dac-converter-tutorial-cpld.html
https://www.diyaudio.com/community/...ac-using-tda1541a.79452/page-453#post-7764267
Antonio
https://electrodac.blogspot.com/p/i2s-to-pcm-dac-converter-tutorial-cpld.html
https://www.diyaudio.com/community/...ac-using-tda1541a.79452/page-453#post-7764267
Antonio