Building the ultimate NOS DAC using TDA1541A

That R302 3k9 between WS and +5V... first time I see that if I am correct in the Grunding DEM mode. The Grunding mode is cleary biased with -15V as usual here also ?! Is there something to close is order it works better ?
Groundig just implemented circuit from Philips book (or Patent judging by the font markings below the figures?)
Yes there is a difference with that R conn. to +5V.
grundig dem.gif


PhilipsDEMinfo1.jpg


BTW
does anybody have whole Philips paper or book or else from where these 2 pages are extracted?
Or some information about the publication?
I searched in few Philips books on digital but couldn't find the se pages...
Thanks
 
Didn't know it was initialy from Philips. In their flagship iirc, back then Grunding not used the SAA but a japaneese filter with the minimal frequency adviced against noise in the Philips book that was not exactly 44.1 x4, but started at 151.x if I am not wrong (surely no difference to be heard with ears between both as pretty close), anyway both close to 200 K hz when using usual free DEM clock option with a cap.

Have you the long Philips book about the TDA1541A, I would be glad to have it for my education, will be appreciated. Was seen in PDF....
🙂

Edit thanks for fig 18 ! 🙂
 
That R302 3k9 between WS and +5V... first time I see that if I am correct in the Grunding DEM mode. The Grunding mode is cleary biased with -15V as usual here also ?! Is there something to close is order it works better ?

No Idea. This device is a fairly "late" Grundig TDA1541 design (1991-1993), so I think there are some "lessons learned". Download the service manual for the unit.
Here are pins marking and order for the predecessor 14Bit TDA1540
Ih has just one GND point on 6 pin.

Yes, but TDA1541 is stereo and a later 16 Bit IC.

And 3 DEM bit more MSB (10) than TDA1541A

Yes, they had to use more active DEM dividers, as the IC tech was not up to that many multi emitter dividers. IC Technology developed very rapidly back then.

(7 dem bits per channel), probably because od dense pac in tha same DIP28 package?

TDA1540 is mono, 14 Bit. You need two for stereo. it goes back to 1979 for pre-production tape out and 1976 for initial prototypes.

TDA1541 was developed because the CD ended up 16 Bit and only appeared in volume in 1986. So it had almost a decade of process IC development more than the TDA1540.

Thor
 
I think the TDA1541A to be a better unit than the TDA1540 (though I just have it in a Marantz cd player) , but with their trick to make it sorta 16 bits with the with the SAA7030, I would be curious to benchmark both on a very "subjective blind test" but to make iso test with a same FGPA for the upsampling front end. Let say a normal european made tda1541A, not a S1 (S2 I never had) or a late Taiwann 1998 that has my preference today)

Many nice guys here made some efforts towards this about FGPA and those chips,, whatever the final pcb layout has to be be enhanced imho; @miro1360 gave a lot to the comunauty : https://electrodac.blogspot.com/p/tutorial-how-to-programm-altera-cpld.html

Ah those serbians, Czechians,Bbohemians, have very good engineers schools ! 🙂
 
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In their flagship iirc, back then Grunding not used the SAA but a japaneese filter

It's more complex than that. It's Grunding CD-9009 Fine Arts. It uses two interleaved TDA1541 to operate at 8 X Oversampling:

Staggered_1_sony_folder_1.jpg



DEM sync is obviously 176.4kHz so within Philips recommendations.

1723133669247.png


1723134049306.png

Have you the long Philips book about the TDA1541A, I would be glad to have it for my education, will be appreciated.

I had the xerox, all of it typewriter written. Never got around to scan it, it was lost in multiple moves across countries and continents.

Was seen in PDF....🙂

Really, I WANT!

FWIW, I looked at any TDA1541 service manual I could find to see if anyone treats DGNG & AGND separate. My findings:

Philips/Marantz/Sony and all those directly using their platform link all grounds and do not separate AGND & DGND, even Sony in the DAS-R1. In PRINCIPLE Philips engineers should know different, but it seems with these huge corps' there are just too many firewalls. US & JP brands just followed Philips/Marantz including even very quality dedicated JP brands like Nakamichi and Micro.

Small British brands (Cambridge, Quad, Arcam etc.) are all over the place. Many separate Analog/Digital but every one is different. I have seen examples with DEM filter capacitors returned to a separate DGND and not AGND. It seems they blindly messed with the different pin's, without clear understanding of how stuff works.

German/Swiss seem diligent and must have read the huge tome multiple times. Grundig, EMT, Studer/Revox all separate AGND and DGND though how consequent etc. varies.

The 1991 Grundig designed Philips satellite radio tuner seems the most clear and consequent at a time when Philips had replaced the DAC2 platform (SAA7220/TDA1541) with the Delta Sigma DAC3 SAA7321 which in turn cleared the way to more delta sigma all the way to DAC7 (TDA1547).

Subsequent designs with TDA1541 never again, IMNSHO achieved similar levels of attention to detail.

Where does that leave us?

+5V/DGND and -15V/AGND are Dr Dre*


* "Still, n....s run up and try to kill at will
But get popped like a pimple,
so call me Clearasil"

Meaning "Clear as Clearasil!"

DEM Cap's etc. is also pretty clear.

For -5/6V, decoupling to AGND but DC loop to DGND!
WTFudge! And is it -5 or -6V. What's up wit' dat!

Seems non too critical in the end. It's inherited from the TDA1540, but non of the public domain sources contain any hint what the bleedin'-5V are for!

On the other hand, originally DEM Filter capacitors according RJvdP went to -V:

1723136072956.png


1723136144582.png


By the time the real TDA1540, despite minimal difference to the actual circuit design the DEM capacitors end up at GND.

I have reasons to believe that in the day of single layer PCB's this had more to do to allow customers workable layouts than actually being the optimum solution.

By the time the TDA1541 taped out (I guess in those days it was "tray out") and when 2 layer PCB's and surface mounted components were no longer exotic stuff for extreme mil-spec only RJvdP was no longer on the team and the people involved in making the TDA1540 tech into a stereo 16-Bit DAC never went back to the original sources and just left it as they found it.

Just an educated guess, but I remember how hard it was to get ANY information in the 80's. Getting Microfiche copies of obscure Journals from libraries and getting them xeroed to paper was expensive and took month. To even KNOW the journal to request was a big deal.

Thor

Some light reading for the beach, if you are interested in working with TDA1541.

https://www.mvaudiolabs.com/wp-cont...-Matching-for-High-Acuracy-Monolithic-DAC.pdf

https://www.mvaudiolabs.com/wp-content/uploads/2022/10/A-Monolithic-14-Bit-DA-Converter.pdf

https://www.mvaudiolabs.com/wp-content/uploads/2022/10/A-Monolithic-Dual-16-Bit-DA-Converter.pdf
 
Many nice guys here made some efforts towards this about FGPA and those chips,

FPGA/CPLD is just a way to shrink this:

1723138068841.png


Onto a Chip.

To some people "FPGA" is some kind of magic that magically makes everything better.

There is no place for magical thinking in tech and war.

It is debatable if this "programmable gate array" logic is a better choice than either real hardware (which may be optimised over the above pictured) or some form of MCU, be it a "hardware equivalent" type like Transputer/XMOS or a multithreaded RISC CPU (e.g. ARM Cortex). In all cases except hardware programming is needed and the matching validation.

For mass production 100's and 1,000's programming is definitely the choice. But added jitter is substantially more than hardware, so we add hardware to cancel the jitter.

DIY? If I had the inclination to make something for "DIY" and not just myself, I'd go with hardware. It gives the most direct control.

I will use this instead:

1723138493225.png


(minus SAA7220)

Because I am very lazy.

Thor
 
Thanks.
Ahahaaa, Dr Dree ! Instead I wonder if we are not monozukuri touched about that tda1541A !

Wonder id some others ICs ask as well as much cares ? (AD1862, but 2 ICs, bumer about the layout, pcm1702 ? Same, needs two ! PCM63 ? I subjectivly prefered the 1862 ! But since I tried a Taiwann 1998 TDA1541A, I coped to it....
 
Ah yes, shift registers, but all are not able to layout it fine about the pcb (how to link between registers in regard to ground) and the current and jitter things as well... Some DIYs are better than anothers... Here but few guys have not sota level or very low as I have (well very low), but sure some have (time often is missed for them as it is a hobby; of course I do not talk about the very fews who are audio pro; but they are all forgiven when we talk about NLA chips 🙂 )

And still that damned active powersuppply and decoupling caps are heard (whatever it is better or not vis à vis of the layout; sometimes I even do not see any logic with the best practices of decoupling and dielctric in HF, but for sure I have very low tech if not zero knowledge, ears migth be biased also; and it is compensation sometimes on the tonal equilibrium with the rest of the hifi,,so subjective;but I do not know on how sort out both because my (non)tech level.
 
That's what are saying people here but many gave up a little early with the TDA1541A imho. Now the more modern chips are a no go for me because the higher digital front end speeds that ask even more knowledge .

I liked, inside the NOS limitation philosophy, what what Andrea Mori diyer, semi-pro now, about the SC-Cut crystals to manage the TDA1541A for instance with low 5.5Mhz SC-cut crystals -from Laptech Canada !-

Not sure I can weigth the poors and cons about NOS with good digital front ends and non interpolation strategies (X2 and more x4 upsampling) though !

Brain for me is more focused on the memory of tonals about the sounds brain knows well : voices, natural acoustics (though fewer and fewer people) over time behavior. Or at least have pain to sort out boths related to what they like best. It is not easy to deal with the high and low frequencies within our ears limits as far as benchmarks occur between two systems.
 
Ah yes, shift registers, but all are not able to layout it fine about the pcb (how to link between registers in regard to ground) and the current and jitter things as well...

Needs someone to make a new generation TDA1541 PCB, optimum layout around TDA1541, I2S-2-SIM hardware conversion, signal conditioning.

Make it with the best suited parts and do a design that can be ordered from JLPCB as completely populated board, minus critical/through hole parts.

If there was a group effort, where everyone contributes a bit of time, it would be easy to do.

Like stone soup.

If one person does all, it is a lot of effort. Then it usually becomes commercial. Or dies before a MVP.

The base schematic has long existed:

DIY I2S to simultaneous converter PCB V2 by ryanj

Switching from 8 Bit 74XX164 shift registers to 74XX16374 16 Bit parts with much better Vcc/Vss pinout in TVSSOP will improve the results. Not many IC's left after this, giving 3 IC's instead of 6 with cleaner power.

Add another 74XX16374 to re-clock all outputs:

DEM_SYNC+
DEM_SYNC-
DL+
DL-
BCKL
LEL
DR+
DR-
BCKR
LER

DEEM followed by Tubee Circuit (DEM Sync assumes Fdem = 4 X WCK)
Others followed MVAL diode clipper signal conditioning

TDA1541 "optimum" setup with local decoupling based on keeping the power supplies to the user, but making them uncritical.

Local I/U conversion with current conversion using 500R to +5V and 4mA bias current from -15V.

It will give 2V P-P and -3V bias.

So we can use a wide range output stages, solid state, tube, passive stepup with transformers...

And still that damned active powersuppply and decoupling caps are heard

Anything in any circuit can be audible, layout even.

Thor
 
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It is debatable if this "programmable gate array" logic is a better choice than either real hardware (which may be optimised over the above pictured) ...
CPLD is "real hardware". If you replicate logic ICs into that, it can work without oscillator exactly like the original circuit - actually even faster with lower "intrinsic" jitter 🙂
Here will be example for DIY community how to do CPLD "schematic based" - without writing code. It is clocking on external clocks (BCK, LRCK) and oscillators are for reclock - removing jitter from original BCK and LRCK.
https://www.diyaudio.com/community/...st-tht-i2s-input-nos-r-2r.354078/post-7755211
 
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Needs someone to make a new generation TDA1541 PCB, optimum layout around TDA1541, I2S-2-SIM hardware conversion, signal conditioning.



If there was a group effort, where everyone contributes a bit of time, it would be easy to do.

Like stone soup.

If one person does all, it is a lot of effort. Then it usually becomes commercial. Or dies before a MVP.

The base schematic has long existed:

DIY I2S to simultaneous converter PCB V2 by ryanj

Switching from 8 Bit 74XX164 shift registers to 74XX16374 16 Bit parts with much better Vcc/Vss pinout in TVSSOP will improve the results. Not many IC's left after this, giving 3 IC's instead of 6 with cleaner power.

Add another 74XX16374 to re-clock all outputs:

DEM_SYNC+
DEM_SYNC-
DL+
DL-
BCKL
LEL
DR+
DR-
BCKR
LER

DEEM followed by Tubee Circuit (DEM Sync assumes Fdem = 4 X WCK)
Others followed MVAL diode clipper signal conditioning

TDA1541 "optimum" setup with local decoupling based on keeping the power supplies to the user, but making them uncritical.

Local I/U conversion with current conversion using 500R to +5V and 4mA bias current from -15V.

It will give 2V P-P and -3V bias.

So we can use a wide range output stages, solid state, tube, passive stepup with transformers...



Anything in any circuit can be audible, layout even.

Thor

Yes about the collective effort. But it can be disapointing, I remember having spent nigths to "coach" a thread I rebornt with some energy about that RyanJ guy but individual natural behavior came again, the guy took the ideas, make a bad layout because he thougth he had it all, choose a stupid pcb name, eventually sold it and the legacy D3 is not very good legacy either but have eventually follower blah people. Back then a few group of 3 guys here, disgusted about the behavior and "stupidity" of the guy, had the idea (I had the conceptual idea) to ask a established designer and brand to make something for the communauty, then the AYA 2 2014 was relaunched with some of our ideas to link to a better digital front end (some more options feasible trough uf-l...). The pcb was sold at a fare price by Audial and still is as far I know (Aya5) during limited in time GB. We bougth the pcb as everyone and many people appreciate a better sounding DAC !

Pedja was nice to follow asked byone of the people about my concept (@CFT which was customer of the on shelf and the other one who had an old Aya board @Ceglar the smal group whom exchanged by PM 🙂 )

So I know very well not only here but in my job abou that MOA/MOE things and how it can turns .

I could try to do the pcb with guidance if more clever people like I am like Zoran, Icazar, Bohrok, etc have no time for this...
 
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I have already started making tda pcb a while ago, but this changes things a bit with all the new info...I don't mind starting a fresh, but i have only so-so free time on hands to dedicate.

I didn't really consider i2s to sim, since it's provided as is from jlsounds i2soverusb board, which mvaudio fixed with lyuben. And i have no need for spdif. But, if it's going to be a group effort, i don't mind optimizing it for more use cases. Use tssop shift registers, and with it a stack for chinese amanero clone to save some costs. Rough schem drawings of collected info would be nice, save some time. Also use case considerations, as pcb can be made as a stack for output stages, saves space for example. Perhaps marks reclocking project. I have also considered using more than one tda chip, since i obtained quite a few over time, but as stated, these are getting significantly harder/expensive to obtain, so single it is.
 
CPLD is "real hardware".

Real hardware doesn't need programming before it works, it cannot "forget" it's configurations (I had CPLD do that).
If you replicate logic ICs into that, it can work without oscillator exactly like the original circuit - actually even faster with lower "intrinsic" jitter 🙂

Again, debatable and depends what the original circuit is.

1723143235736.png


This PCB includes a complete CD Player control (left side and bottom, power supply, servo driver IC and CD Processor.

There is quite a collection of hardware, a low jitter clock PLL (top center) , TCXO Clocks (top left), an ASRC operated as SSRC for "Oversampling" (TSSOP IC near the CPLD), power supplies and not the least a CPLD.

I have worked in a fair few designs with CPLD and FPGA and they are neither low jitter nor inherently superior to discrete logic. That's just magical thinking or zweckoptimismus (this german word has no english equivalent).

As said, they are easier for mass Production where complex circuits are needed.

In the above design the CPLD added so much jitter over and above a PLL Clock Generator (which is hardly femto seconds to start with) that a 74ACT174 re-clocker was needed after it.

If a CPLD or FPGA replacing a discrete logic circuit lowers jitter, I have my doubts about the design and implementation competence of the original.

Thor
 
i have only so-so free time on hands to dedicate.

#me2

I didn't really consider i2s to sim, since it's provided as is from jlsounds i2soverusb board

Which cannot be connected via SPDIF which remains the lowest common denominator. I have multiple sources with SPDIF that would want connecting, from BT Receivers to TV's.

WM8805 gives very low jitter from SPDIF, implemented correctly. Shame cirrus nixed it.

I guess an Si5317 in narrowest bandwidth mode could be added as jitter cleaner So any I2S source can be used.

Use tssop shift registers

Too big.

TVSOP and use 16 Bit parts. Like this:

Texas Instruments SN74AUC16374DGVR

I know, AUC logic is aggressively low voltage, but it has advantages that make it worth it.

TDA1541 wants to see 250mV P-P swing around ~1.3V offset anyway, so whatever logic runs on at least 2.6V will be fine.

Make it all in AUC logic running at 2.6V.

and with it a stack for chinese amanero clone to save some costs.

Good call.

Rough schem drawings of collected info would be nice, save some time. Also use case considerations, as pcb can be made as a stack for output stages, saves space for example. Perhaps marks reclocking project. I have also considered using more than one tda chip, since i obtained quite a few over time, but as stated, these are getting significantly harder/expensive to obtain, so single it is.

We can do two things:

Make a pure digital PCB including CS8416 SPD In; SI5317 jitter filter (or whatever out there is better) and footprint for any Amanero format input circuit from Aliexpress to ultimately SMA (I hate FL connectors) connectors so we get coax to TDA1541. Board offers balanced simultanious out from any I2S source up to 384kHz and for two TDA1541. Leave TDA1541 itself completeltly open, or make separate TDA1541 only PCBs.

Make an "all in one" with a second breakoff/plugin TDA1541 PCB and the ability to offer SE and BAL options.

I still like stuffing options for either 50/60Hz DEM clock or 4 X Fs or fixed clock as MCK (512X) / 16, as both options can be optimised.

Especially now we know that AGND and DGND can stay pretty much completely separate, running the DEM in "Fast/Sync" mode should reduce the problems we see in suystems with mixed (up) ground.

Thor
 
Which cannot be connected via SPDIF which remains the lowest common denominator. I have multiple sources with SPDIF that would want connecting, from BT Receivers to TV's.
Which is why i said it was currently only me project, and that i don't mind redoing it for broader audiOence and more use cases 🙂

Make it all in AUC logic running at 2.6V
Makes sense.
Make a pure digital PCB including CS8416 SPD In
Wm8804/5 is still i belive up for factory order till end of the year, since it's not going to be commercial project, i belive it should be it, as it's still available in sufficient quantities. I have already stated it's superiority in miros thread. I don't mind buying a stash for future endeavor diy-ers, but tda is getting harder and harder to obtain, there probably won't be many more tda dac builders few years down the road.

We can do two things
Ohh i love making modular designs, so stackable tda would be quite nice. But additional logic/complexity for true differential?
 
For -5/6V, decoupling to AGND but DC loop to DGND!
WTFudge! And is it -5 or -6V. What's up wit' dat!

Well, I found something:

Inside Classic Audio Arcam Delta Black Box 2

For reasons unknown to me, a handful of high performance devices supplied -6V to the -5V power input (VDD1). The DAC IC will tolerate this in the short term, but over time every TDA1541A supplied with -6V to VDD1 will fail.

So, -5V. Good. One more mystery resolved by the service tech. Likely deliberately build in lifespan limitation.

Thor