No idea, what you show is not really related to what I showed, even if superficially it might seem so.
Thor
Thanks Thorsten. Have you simulated the distortion?
In that circuit (my attempt), the increase in distortion for high frequecies is caused by the capacitance at the input, 300nF.
In that circuit (my attempt), the increase in distortion for high frequecies is caused by the capacitance at the input, 300nF.
Yes.
Did you simulate SNR?
This capacitance depends on the circuit.
The Sziklai pair is a feedback circuit. I suspect that excessive capacitance causes instability, that shows up as increase in HD and also as reduced 20Hz -20kHz SNR.
As realistically everything here starts at 100's of kHz I wonder if we have one of Spice's blind spots.
FWIW, you should get < -90dB H2.
The lowest possible capacitance that doesn't cause huge impedance peaks usually causes a minimum rise in HD that keeps HD below -90dB.
This behavior will be worth testing different capacitor values.
Thor
Beliefs & Superstitions ???? LOL The thing about playing with TDA is that everything that my curious finger sticks into made differences
in sound be it good or bad results. Hence my dac is always on breadboard.
Thks again
I found two methods: visually minimize the error between two digital steps, or minimize the distortion caused by the error between the steps.
First method:
https://www.diyaudio.com/community/threads/dac-linearity-test-cd.113620/
Second method:
https://www.diyaudio.com/community/threads/tda1541a-reducing-dnl.414159/
Sorry, it doesn't.
You have still 4 distinct currents that are non-equal and require averaging for each bit. That is how the TDA1541 works. You MIGHT be able to ditch the averaging capacitors if running DEM at 4 X Fs or greater, but as John Brown remarked, that adds a mighty RF noise source.
Though based on a more complete understanding of the ground and supply assignments some of the negative effects from a high DEM Clock can be reduced.
What @lcsaszar does is to reduce the already low non-linearity further.
Thor
And I have to add, usually the THD at full scale is dealt with, or THD at -60dBFS or whatewer low level. My problem with such measurements is that these are done around analog zero level only, that is digital 32767/32768. This corresponds to the bit #15 change from 0 to 1. However, low level distortion (cased by differential nonlinearity) occurs around every bit change, not only around bit #15. We can measure THD around bit #10, bit #11 and so on, with a -60dBFS signal, by bit shifting to the level to be measured. I am not sure I could explain it clearly, perhaps I will create a drawing. In any case, the data sheet specifies DNL, differential nonlinearity in terms of fraction of LSB that can be directly measured (and compensated) with my method around each bit transition where the bit currents are accessible at the DEM decoupling pins, i.e. at bits #9 to #15.
@ThorstenL I've referred to this comment of yours. IHMO having H9 at the level of H2, which MV graphs suggest for I/V~10R, does not look like a good idea even if the absolute level is low.
It is on my plan to take FFT spectra with various I/V resistors at full scale, using a zero distortion digitally generated dithered sine wave. 0 Ω, 10 Ω, 33 Ω, 100 Ω, with and without the -2 mA idle current compensation.
The real world results woul;d depend on the following IV stage as well but still a worthwhile exercise.
Might I suggest a 75r resistor between 33 and 100?
SNR is very high, with non ideal CCS and models from Bob Cordell (with realistic base spreading resistance). It shows a very clean output even for 1nA current input.
It will be very difficult to obtain such a SNR in the real circuit, of course.
Get a 10-Turn 200 Ohm wire wound pot with a vernier dial. Dirt cheap on Ali and once calibrated you can just dial up resistances easily.
Thor
It rapidly reduces as we add capacitance and thus noise gain.
Of course.
Thor
For an open loop (or compound transistor) output stage getting > -100dB H2 will be challenging.
At 10 ohm the HD is ~ -120dB. Even H9 will be inaudible/masked...
As we go below 10 Ohm (say 0.4 Ohm) all harmonics take a steep dive, only H2 (good) and H5 (bad) have a fairly flat profile.
Thor
I came across a satellite radio tuner from Philips (Grundig Fine Art level design - Philips 70ft990 DSR Tuner) that showeshow they handled power supplies.
For sure, Pin14 runs back towards the digital part and decoupling to pin 28 with no obvious link to pin 5 anywhere near the TDA1541:
GND A & GND D only link on the power board and are completely separate otherwise.
Notabene, -5V is treated as ANALOG supply (and actually -6V), but the actual power comes from the same winding as +5V D!
Calling the effort on the -6V supply vestigial is charitable. And it is not tapped off from -15V.
On the other hand, -15V uses an LM2990-15 which in those days counted as "premium" regulator.
Seems both but mainly a DC pin setting reference. Given it is linked to AGND here it suggests it doesn't make much noise.
The very basic power supply (and the high PSRR) suggests this unit is not very consequential for the audio or digital side.
Analogue and separate.
And it is absolutely clear that DGND and AGND are completely separate and linked only for DC.
So we can with a high degree of confidence conclude:
DGND & +5V D form a power pin pair. For this pair DGND is the "reference" for signals and power. Most annoyingly, +5VD is also the pin that carries the complementary current of the Output which is it's only analogue function.
AGND & -15V A form a power pin pair. For this pair -15V A is the "reference" for signals and power and AGND is actually the positive Power supply, as the entire circuit between AND & -15V is almost exclusively composed of NPN transistors.
The -5/-6V seems not particularly either digital or analogue. It draws the highest current of any pin though. More information is probably needed. But for now I call +/-5V still part of the same loop, with +5V being the collection rail for analogue currents as it needs to link to -15V for analogue decoupling.
So:
DGND & +5V D - treat as digital, with extra LF decoupling to -15V.
-5V/-6V decouple to +5V only
AGND & -15V A - treat as analogue/rf supply, -15V A is the actual collection / reference rail for analogue currents.
Thor
@ThorstenL
Mucho thanks about the notes on PS pins.
So Vgnd(d) not refering to DGND, because it will be self-refering operation without representing other then itself.
In theory it caled simulation... 🙂
🙂
So, for noe we can continue in the matter of power supplies:
a) -15V => AGND as -15V is true analog reference pin.
b) -5V best guess, DC and digital CCS common.
c) +5V MOSTLY digital but also carries the complement of Iout.
d) Based on internal Circuit details published, AGND/-15V are one pair, DGND/+5V are another pair and -15V is kinda at loose ends but really loops to +5V.
"and -15V is kinda at loose ends but really loops to +5V."
You mean -5V instead of -15V ?
From all of that it somehow imply that configuration of power transformer, rectifier system have significant role?
Also i always when i was used a shunt end close to the chip rezults was somehow better?
I think that transformer for this Analog part -15V of power supply, should be with CT, (full-wave rectifiers with 2 diodes), that one with pure analog separate transformer with core to connect to chases ground and the screen shield between Prim-Sec.
That CT should be connected to AGND pin and corresponding PCB layer. With Shunt end close to chip.
Same for the +5V as for most digital part.
For -5V I am not sure... 🙁
PS I didnt read the Lat post from Thor, so this post is writen prior his commens above in the post and posted latter...
Thanks 🙂
Mucho thanks about the notes on PS pins.
Actually boot are a different representation of same pin... Vgnd(d) and DGND...
So Vgnd(d) not refering to DGND, because it will be self-refering operation without representing other then itself.
In theory it caled simulation... 🙂
I think about checking in PS grounds without the DAC chip inserted. In case of separate PS? But thanks for the idea how to check with the dac placed in circuit.
🙂
So, for noe we can continue in the matter of power supplies:
a) -15V => AGND as -15V is true analog reference pin.
b) -5V best guess, DC and digital CCS common.
c) +5V MOSTLY digital but also carries the complement of Iout.
d) Based on internal Circuit details published, AGND/-15V are one pair, DGND/+5V are another pair and -15V is kinda at loose ends but really loops to +5V.
"and -15V is kinda at loose ends but really loops to +5V."
You mean -5V instead of -15V ?
From all of that it somehow imply that configuration of power transformer, rectifier system have significant role?
Also i always when i was used a shunt end close to the chip rezults was somehow better?
I think that transformer for this Analog part -15V of power supply, should be with CT, (full-wave rectifiers with 2 diodes), that one with pure analog separate transformer with core to connect to chases ground and the screen shield between Prim-Sec.
That CT should be connected to AGND pin and corresponding PCB layer. With Shunt end close to chip.
Same for the +5V as for most digital part.
For -5V I am not sure... 🙁
PS I didnt read the Lat post from Thor, so this post is writen prior his commens above in the post and posted latter...
Thanks 🙂
Here are pins marking and order for the predecessor 14Bit TDA1540
Ih has just one GND point on 6 pin.
And 3 DEM bit more MSB (10) than TDA1541A (7 dem bits per channel), probably because od dense pac in tha same DIP28 package?
Interesting I didnt know by now (somehow i miss the info) that TDA1540 has OP inside for frequency compensation at pin 5 which has to be remain unconnected.
Ih has just one GND point on 6 pin.
And 3 DEM bit more MSB (10) than TDA1541A (7 dem bits per channel), probably because od dense pac in tha same DIP28 package?
Interesting I didnt know by now (somehow i miss the info) that TDA1540 has OP inside for frequency compensation at pin 5 which has to be remain unconnected.
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