Thanks Thorsten for sharing.
I understood it all, with the exception of the JFET compounds. Could you explain them in detail? I don't get how they work.
(BTW I understand the BJT compound).
Thanks,
Alex
I understood it all, with the exception of the JFET compounds. Could you explain them in detail? I don't get how they work.
(BTW I understand the BJT compound).
Thanks,
Alex
Did You tried ES9008, first model? Current mode. Somehow I think that sounds better from all other ES. I dont know... I didnt compare directly... I used also 100MHz clock.
Understood bro what Im saying is whatever input impedance from input of trafo i/v stage the output impedance will be multiplied hence.
The other issue is voltage gain with no current gain will never driver the music well, this I've proven to myself with lots of experiments.
Hi Thorsten do You know maybe what difference is allowed from DGND (pin 14) and AGND (pin 5) pins on TDA1541A?
Hi Thorsten if I may, what are your thoughts on this thread https://www.diyaudio.com/community/threads/tda1541a-reducing-dnl.414159/
Thks
Thks
I just found it 🤢
it is min -0.3V and max +0.3V
.
Maybe put two reverse polarised Germanium diodes between DGND and AGND?
Please note that the voltages on the conceptual schematics of the TDA1541A in the opening post are written in reverse order. Also you can't measure the voltages directly because the input resistance (usually 10M) of the measuring instrument falsifies the actual value. I used the compensated bridge method.
🙂Yup that what I answered. Buffer is your friend😊
Buffer with 10 factor13 Z input and enough current are not rare ! Not a problem, imo. I somewhat found in love in this little ic for that because not too expensive and very neutral, it is the little less expensive brother of AD797 : AD8597. Feed it with your fav power rail caps, the ic has very "no sound" on his own ! Of course, there are also 200 mA op amps if you need it or want to use low impedance headphone for instance ! I use it in 4 layers pcb I made for the AD1862 with another ic for the I/V task.
cheers
Here's my dual 1541 DAC. Input is spdif direct from a Behringer UAC222 into a SRC24/96 set to upsample to 96Khz, and output from the Sowter transformer into the 22k input Z of the UAC.
Show me where the frequency reponse is influenced by the inductance, and relatively low load impedance.
Green line is phase.
Rather than all the theory and opinions, I like to present actual results.....
Show me where the frequency reponse is influenced by the inductance, and relatively low load impedance.
Green line is phase.
Rather than all the theory and opinions, I like to present actual results.....
Attachments
Interesting. That would suggest that the harmonics profile posted at MVlabs corresponds to listening experiences (I do not agree here with Thorsten that the level matters more than the harmonic profile). I also remember reading reports from early 2000's where ppl preferred higher R.
Apologies Icsazar no punt intended, appreciate your experiment & sharing with us of your findings. The reason that I brought up your thread here is since
we're able to null the differences on the DEM pins, would that negate the need of using big capacitors or if we can take your ideas & expound on it further.
Cheers
It is deliberately drawn a little misleading. It is the same as a simple Darlington, but with a J-Fet. As the J-Fet has a limited drain source voltage, it is powered by a zener diode. How this diode gets it's current without allowing "current escape" or adding extra current AND being able to have the circuit start is the magic trick, I wish to keep hidden. Sorry.
But functionally it's just a Darlington with an N-J-FET instead of first NPN in redux.
I never even had the EVM.
Where did you find that? Curious.
Thor
Interesting.
Seeing TDA1541 well implemented is -95dB THD&N and -110dB SNR at digital silence, which is adequate for 18 bit @ 96kHz (dithered at 384kHz - not that anyone made CPLD code for it, though trivial), I will question the purpose though.
Thor
I do not agree with this guy either. Wait, that's supposed to be me? No, I was not talking about level.
Thor
In the datasheet?
But Vgnd(d) signed with "-" is that telling us that only negative PS are digital part
And Vgnd(d) is refering to +5V?
So that is obviously if the power suplies are separate. BUT which one or ALL of them.
+5V is digital for sure?
-5V ?
-15V ?
So if we can be for sure what the suplies are D and A, we can left open connection with AGND and DGND and measure eventual difference?
I dont know if it is from the importance but GND(D) is close to Vdd2 -15V (to decouple)
That can implicate that -15V is digital PS?
Also GND(A) is closer to AOR and AOL, somehow logical. But next close to Vdd1 -15V and Vdd +5V
.
The pins are far away from each other, diagonal, are Vdd and GND(D) which has to be closest to decouple?
Last edited:
You still need appropriate filter capacitors (decoupling in Philips' terms) according to your taste, beliefs and superstitions.
I could use one A23 alkaline battery to achieve low current escape, circuit below. Single digit nanoamp base current modulation on Q2. The circuit is biased by I1 which is 10mA, the signal is I2 which is 2mA P-P. The squarewave looks good with 300nF+200mohm.
HOWEVER, the simulated distortion is high, second harmonic is 60dB down from the fundamental (10 KHz). This shouldn't be, it doesn't make sense. What's happening here?
Last edited:
Too many floating around, it's not in the ones I have.
No, it is not.
It is:
Vagnd - Vdgnd = -0.3V ... + 0.3V.
No. It's just a line break.
No, it is referring to DGND.
I will agree, based on that.
Based on internal Circuit details published, AGND/-15V are one pair, DGND/+5V are another pair and -15V is kinda at loose ends but really loops to +5V.
No, it is MOSTLY digital but also carries the complement of Iout.
My best guess, DC and digital CCS common.
= True Analog Reference Pin
We can, but the risk is a dead chip.
We know no power pin draws > 50mA, so if we connect a resistor of 0.3V/50mA = 6 Ohm between the grounds (say 3R3 to be safe) we can measure current.
No, Vdd (+5V) and Vss (DGND) are placed in line with standard practice for (TTL/ECL) the logic IC of the era (still observable in modern 74HCXX CMOS logic).
No.
Not really.
All TTL pinout derived IC's are like that.
Compare 74HC74 to 74ACT11074.
Thor