Hi John,
I've been following this thread for a long while now, dropping in comment of my own from time to time, and I just felt compelled to say that I think you represent an outstanding example of a DIY contributor. You have innovative circuit ideas, have evaluated them in real circuit implementations, reveal complete schematics of those circuits, and provide detailed descriptions of how those circuits function and of your thinking behind their creation. The only other 'expert' contributors who are as freely open with their intellectual property, and who readily come to mind, are Nelson Pass and Thorsten Loesch. August company, for sure. 🙂
I've been following this thread for a long while now, dropping in comment of my own from time to time, and I just felt compelled to say that I think you represent an outstanding example of a DIY contributor. You have innovative circuit ideas, have evaluated them in real circuit implementations, reveal complete schematics of those circuits, and provide detailed descriptions of how those circuits function and of your thinking behind their creation. The only other 'expert' contributors who are as freely open with their intellectual property, and who readily come to mind, are Nelson Pass and Thorsten Loesch. August company, for sure. 🙂
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Indeed, those people are outstanding, John Brown and Salas DIYers and Nelson Pass and Thorsten Loesch the professionals.
I second that! or in this case 3rd or 4th that!
Thanks to people (Gurus) like them that makes this music/audio hobby that for fun 🙂
Peter
Thanks to people (Gurus) like them that makes this music/audio hobby that for fun 🙂
Peter
John, are you using the same cap value for DEM (between the two DEM pints) as specified by the datasheet? (I think 680pf)
How does the size of this cap influence behaviour?
How does the size of this cap influence behaviour?
Hi studiostevus,
No, data sheet application results in approx. 200 KHz DEM clock rate, I need 2.8224 MHz, this requires a lower timing cap value.
The capacitor value determines the DEM oscillator frequency. If this frequency differs to much from the target value (2.8224 MHz) the DEM oscillator cannot be synchronized with BCK.
John, are you using the same cap value for DEM (between the two DEM pints) as specified by the datasheet? (I think 680pf)
No, data sheet application results in approx. 200 KHz DEM clock rate, I need 2.8224 MHz, this requires a lower timing cap value.
How does the size of this cap influence behaviour?
The capacitor value determines the DEM oscillator frequency. If this frequency differs to much from the target value (2.8224 MHz) the DEM oscillator cannot be synchronized with BCK.
Hi maxlorenz,
TDA1543 output circuit is different from TDA1541A and needs no current buffer.
I attached schematic of a TDA1543 DAC with DC-coupled outputs and passive I/V conversion.
This is the best performing (and easiest to build) TDA1543 circuit I designed so far (tested on MK9 prototype setup with latest timing module).
R1, R2, D1 ... D6 are WS / DATA limiters (1.8Vpp).
C1 is a 1uF 1210 SMD film cap soldered directly to TDA1543 pins 4 and 5 as close to the plastic housing as possible.
R3 and R4 are passive I/V resistors that offer approx. 0.0025 * 820 = 2.05Vpp output signal.
P1 is passive I/V resistor bias voltage (adjust to 3.2V).
P2 provides DC-coupled outputs (no coupling cap required). Adjust P2 for lowest DC offset on R and L outputs. This would give around 2.2V on the wiper of P2.
TDA1543 requires a super clean 5V power supply (balanced or battery power supply) and ultra low jitter BCK signal with white noise residual jitter spectrum.
Does not this design work well with dir 9001?50ps jitter?Does not it a better design than regular tda1543 circuits around?I do not need extreme well design,just not want output caps in tda1543 design and try it.
The latest power supplies consist of rectifier, capacitance multiplier, balanced passive RC filter and shunt regulator. This configuration offers very clean DC voltage even with highly polluted mains voltage (attached schematic).
John
how do you compare your last discrete shunt regulator posted here with led referenced regulator posted http://www.diyaudio.com/forums/digi...e-nos-dac-using-tda1541a-297.html#post1884018 either measure bandwidth and impedance and perceived sound
I am trying to get my latest version to work. I am using the same divide-by-4 circuit using 2 flipflops as John does, as well as his i2s attenuator and (what I believe to be) his DEM reclock circuit. Source is a squeezebox, driven by the masterclock (different design than John's but works).
Unfortunately I am hearing white noise when I press play (otherwise dead silent). So, I press play, and full scale white noise shows up on the outputs. I press stop, and it is nice a silent. So I am thinking the output works correctly, the dac works, but there is something with the digital inputs to the TDA1541a.
Looking at my scope, the BCK signal is a nice square, WS is a nice square, and DATA looks as it should. Nothing that seems out of order. I don't have a logic analyzer, so I can't really look at that though. What could be wrong?
DEM reclock signals are a bit odd though. I have DEM soft-synched with BCK (to pin 16) and a 10nF cap between pin 16 and 17. I think this cap value is too low, but I don't think it is the source of the white noise, is it? I would assume that if DEM reclocking doesn't work, I still get music, just noisy/distorted.
Can somebody give me some pointers on what I should be looking at?
Unfortunately I am hearing white noise when I press play (otherwise dead silent). So, I press play, and full scale white noise shows up on the outputs. I press stop, and it is nice a silent. So I am thinking the output works correctly, the dac works, but there is something with the digital inputs to the TDA1541a.
Looking at my scope, the BCK signal is a nice square, WS is a nice square, and DATA looks as it should. Nothing that seems out of order. I don't have a logic analyzer, so I can't really look at that though. What could be wrong?
DEM reclock signals are a bit odd though. I have DEM soft-synched with BCK (to pin 16) and a 10nF cap between pin 16 and 17. I think this cap value is too low, but I don't think it is the source of the white noise, is it? I would assume that if DEM reclocking doesn't work, I still get music, just noisy/distorted.
Can somebody give me some pointers on what I should be looking at?
I tried 33pf first, but didnt work...
I also tried another DEM reclock scheme (mk7)...
But I don't think it's the DEM circuit that is the problem here... do you?
I also tried another DEM reclock scheme (mk7)...
But I don't think it's the DEM circuit that is the problem here... do you?
Don't know exactly your schema, but DEM it's very critical... Be sure too that -15Vdc is exactly -15 to -15.8 not less, if not you will hear distorsion and noise...
I suggest to get rid of the dem reclocking and just try a 470pf cap between pins 16 and 17.
This will determine if the problem lies with dem or i2s.
This will determine if the problem lies with dem or i2s.
I did, and it's not DEM (if DEM was not working, I would still get some music I believe).
Supply voltages to the TDA are correct.
The chip is still functioning.
The squeezebox is working and receives 11Mhz masterclock signal (SB internal dac works).
Supply voltages to the TDA are correct.
The chip is still functioning.
The squeezebox is working and receives 11Mhz masterclock signal (SB internal dac works).
I also tried adjusting BCK levels (I have a trimmer installed). I clearly see that if BCK(high) goes below a certain voltage, there is no output on the dac. If I then turn up the voltage again, output comes back (white noise).
Do you have ground connected between squeezebox and dac board? You will need a common ground. I think this is the problem
Do you have ground connected between squeezebox and dac board? You will need a common ground. I think this is the problem
I have common ground...
Have you ever run i2s to the dac without attenuators, and it worked?
I had it working on an earlier version, including attenuators.
The SB is 3.3V, so I used the values posted by John earlier (820R to GND, 2k7 to 3V6).... this is the first time I test these values, so not sure.
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