Hi John,
I've been following this thread for a long while now, dropping in comment of my own from time to time, and I just felt compelled to say that I think you represent an outstanding example of a DIY contributor. You have innovative circuit ideas, have evaluated them in real circuit implementations, reveal complete schematics of those circuits, and provide detailed descriptions of how those circuits function and of your thinking behind their creation. The only other 'expert' contributors who are as freely open with their intellectual property, and who readily come to mind, are Nelson Pass and Thorsten Loesch. August company, for sure.
I've been following this thread for a long while now, dropping in comment of my own from time to time, and I just felt compelled to say that I think you represent an outstanding example of a DIY contributor. You have innovative circuit ideas, have evaluated them in real circuit implementations, reveal complete schematics of those circuits, and provide detailed descriptions of how those circuits function and of your thinking behind their creation. The only other 'expert' contributors who are as freely open with their intellectual property, and who readily come to mind, are Nelson Pass and Thorsten Loesch. August company, for sure.
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Hi studiostevus,
No, data sheet application results in approx. 200 KHz DEM clock rate, I need 2.8224 MHz, this requires a lower timing cap value.
The capacitor value determines the DEM oscillator frequency. If this frequency differs to much from the target value (2.8224 MHz) the DEM oscillator cannot be synchronized with BCK.
No, data sheet application results in approx. 200 KHz DEM clock rate, I need 2.8224 MHz, this requires a lower timing cap value.
The capacitor value determines the DEM oscillator frequency. If this frequency differs to much from the target value (2.8224 MHz) the DEM oscillator cannot be synchronized with BCK.
Does not this design work well with dir 9001?50ps jitter?Does not it a better design than regular tda1543 circuits around?I do not need extreme well design,just not want output caps in tda1543 design and try it.
John
how do you compare your last discrete shunt regulator posted here with led referenced regulator posted http://www.diyaudio.com/forums/digi...e-nos-dac-using-tda1541a-297.html#post1884018 either measure bandwidth and impedance and perceived sound
I am trying to get my latest version to work. I am using the same divide-by-4 circuit using 2 flipflops as John does, as well as his i2s attenuator and (what I believe to be) his DEM reclock circuit. Source is a squeezebox, driven by the masterclock (different design than John's but works).
Unfortunately I am hearing white noise when I press play (otherwise dead silent). So, I press play, and full scale white noise shows up on the outputs. I press stop, and it is nice a silent. So I am thinking the output works correctly, the dac works, but there is something with the digital inputs to the TDA1541a.
Looking at my scope, the BCK signal is a nice square, WS is a nice square, and DATA looks as it should. Nothing that seems out of order. I don't have a logic analyzer, so I can't really look at that though. What could be wrong?
DEM reclock signals are a bit odd though. I have DEM soft-synched with BCK (to pin 16) and a 10nF cap between pin 16 and 17. I think this cap value is too low, but I don't think it is the source of the white noise, is it? I would assume that if DEM reclocking doesn't work, I still get music, just noisy/distorted.
Can somebody give me some pointers on what I should be looking at?
Unfortunately I am hearing white noise when I press play (otherwise dead silent). So, I press play, and full scale white noise shows up on the outputs. I press stop, and it is nice a silent. So I am thinking the output works correctly, the dac works, but there is something with the digital inputs to the TDA1541a.
Looking at my scope, the BCK signal is a nice square, WS is a nice square, and DATA looks as it should. Nothing that seems out of order. I don't have a logic analyzer, so I can't really look at that though. What could be wrong?
DEM reclock signals are a bit odd though. I have DEM soft-synched with BCK (to pin 16) and a 10nF cap between pin 16 and 17. I think this cap value is too low, but I don't think it is the source of the white noise, is it? I would assume that if DEM reclocking doesn't work, I still get music, just noisy/distorted.
Can somebody give me some pointers on what I should be looking at?
I had it working on an earlier version, including attenuators.
The SB is 3.3V, so I used the values posted by John earlier (820R to GND, 2k7 to 3V6).... this is the first time I test these values, so not sure.