Building the ultimate NOS DAC using TDA1541A

I don't think Max wants to challenge Nelson! ( Do you Max? ) I think Max is asking why, when Nelson P and John/EC are saying essentially the same thing, ...why are people challenging the latter but not the former? I'm just pointing out that NP makes it clear that he is referring to a small, specialised class of drivers. That makes it hard to disagree with what he is saying.

Exactly. Thanks.
No I would never dare to challenge NP. I am only a diletante .

The question is that IF there is also a benefit with other types of drivers, appart FR.
As I said, I will test it with my own FR plus some UCD ClassD power amp, which has plenty of power to (efficiently) loose, and, apparently, do not care about output impedance (well, sort of).

The experiment is relativelly easy to perform. We are not like Einstein who had to perform "mental experiments" and then wait 50 years for the confirmation to arrive... ;)
This hobby is empyrical after all...

Cheers,
M
 
ECdesigns wrote>

This might be interesting, when I read it, I thought "this can't work". Yet curious as I am, I just tried it for myself. I am still glad I did.
http://www.altmann.haan.de/splif_page/[/QUOTE

Is that idea brilliant or what?
And could have even being thought out without too much electronics knowledge...
Oh, another project to test!
 
Thanks John, and MaxL.

I had forgotten Charles' SPLIF system and with Mercurio's reminder about Nelson's article on 'resistor loading a voltage gain amp', I can see how it all could work. My apologies.

It would possibly require a seperate "Q correction" for each attenuator setting, but that isn't impossible - awhile back, I used some balanced T-network attenuators on horn drivers that avoided all the "dynamic compression" problems (over a 12dB range, I think). A real PIA, tho'!

I have a Hafler amp here somewhere, will try it out.
With my F3 and high % drivers system, there are different constraints!

Mercurio, be interesting to hear what happens with your Autographs - I'm still struggling with the headamp CT P.supply and Regs

Hmmmmm...!
 
Hi James,
Mercurio was the messenger of the gods...and also my regent planet (until Vulcano appears ;) ).

About SPLIF, I talked to Carlos, DX, and he already had tried it with bad results on his amp. I have to find or build another amp to test it...

I thought you had an F5 also...I was thinking about building a pair anyway...

Cheers,
Mauricio
 
Maybe that messenger guy would like to drop in here and impart some wisdom before he knocks off for a rest! - trying o keep up with John requires consiiiiiiiderable effort!

I have added the input attenuators (poor suffering 1541A chip)with good results and now finishing up the boards for the old style reclocking as per your diagram some pages ago with Elso's Kway 7 clock and then the 3 transistor o/p stage.

I was slowly getting the hang of John's development of these chips and even that marvellous idea about the SD reader but the last left turn has me floundering again (as usual!) - so I'm just plodding along for now, but having a bit of fun with the C.T. power supply system - is excellent.

I do much prefer this NOS sound than any of the new wonder boxes, no doubt about it, and it's not just an Alzheimers thing (yet!)!

I upgraded a local F5 but definitely prefer the sound of the F3 with this system and expect further improvement when I get that CT supply functioning properly. Then I just might go completely nuts and add the very hungry Salas' Power Shunt to finish it off!

I'm sorting each of these out with the DOA headamp that draws a reasonable 250mA @ +/- 16v and is progressing nicely on perf board - the pcb design is not complete yet.

Thanks for the Cct and values - made it much easier and other help too,everyone!

John,
a question? Does the 2mA and high Zout from the dac drive the I/P of the power buffer (amp) like the Moskido O.P stage? Or would you still need another driver stage in front?
 
Hi jameshillj,

John,
a question? Does the 2mA and high Zout from the dac drive the I/P of the power buffer (amp) like the Moskido O.P stage? Or would you still need another driver stage in front?

I am using TDA1543 with 680 ... 900 Ohm passive I/V resistor and alkaline 3 ... 3.8V reference voltage (like in the SD-player diagram I posted).

This gives 0.0023 * 680 = 1.56Vpp ... 0.0023 * 900 = 2.07Vpp from a single TDA1543 chip without using the Vref pin.

My power amp has input impedance of 100 K Ohm, and variable gain, so it can be directly driven by the DAC.

This minimizes the amount of components between DAC chip and power amp input.


Elso's Kway 7 clock

It's just a Colpitts oscillator with crystal in parallel resonance (high impedance). The choice of a single JFET isn't optimal either.

Crystal oscillators have a number of "issues". One is the sensitivity to power supply noise. This requires cleanest possible power supply. Elso's power supply still passes noise. This circuit would perform best when running on a battery power supply.

Second problem is that connected loads, like the comparator input, can easily shift (modulate) oscillator frequency. This wouldn't be such problem if the load capacitance was completely constant, but in practice it isn't. So extra phase noise is induced, simply by connecting a single load. The comparator will also produce a large frequency spectrum (fast signal transients), this isn't very desirable.

The phase noise also increases as more (TTL) loads are connected (varying load capacitance and crosstalk from connected loads).


I use a different approach, it's basically a unity gain hybrid buffer, driving a tuned 3rd ... 12th order crystal filter through a phase shifter that includes an inductor. The crystal filter is loaded with correct impedance, and this signal is fed back to the input of the buffer. This way sine waves with very low distortion and high amplitude (approx. 9Vpp at the buffer input with 5V power supply) can be generated. This high amplitude is achieved by the inductor. The oscillator easily produces 4 ... 5Vpp at the buffer output.

This output signal was shaped to have relative fast positive going edge and slow negative going edge, in order to ensure accurate triggering by connected logic circuits (positive going edge), and minimizing interference by a slow negative going edge.

In order to minimize the effect of power supply noise, a battery reference voltage was used to bias the unity gain buffer (I now use a 3V lithium cell that will last as long as its shelf life).

In order to minimize the effect of varying capacitive loads, two separate discrete buffers were added to the oscillator. These buffers were designed for minimum frequency shift with varying load capacitance. In order to achieve lowest possible phase noise, I only connected one single clock load to each buffer.

This way very low phase noise could be achieved, and maintained, with connected loads and practical power supplies.
 
Hi ccschua,

With regards to Passive IV conversion for TDA1541a, ignoring the 25mV compliance, what is your recommended DC battery and resistors value.

The TDA1541A current outputs are constructed different compared to the TDA1543. The TDA1543 allows / tolerates large DC / AC voltages at the current outputs. The TDA1541A does not, here, both DC and ac at the DAC outputs must remain low in order to keep distortion low. The TDA1541A ac output signal will clip at approx. 900mVpp.

When passive I/V resistor value is too low, S/N ratio is poor. So it's best to use max. possible output amplitude while keeping distortion low.

Practical passive I/V resistor values for the TDA1541A vary between 82 Ohm (328mVpp) and 100 Ohm (400mVpp). The I/V resistor is connected between TDA1541A output and AGND (pin 5).

Next, some amplification is required to achieve desired output amplitude.

In order to determine the best performing analogue circuit, the I2S signals must be virtually perfect (extreme low jitter amplitude, flat jitter frequency spectrum, and lowest possible I2S signal crosstalk). With the SD-card player and 12-crystal lithium-cell referenced precision master clock, the passive I/V conversion appears to works best for the TDA1543. The TDA1541A appears to perform best with the trans-impedance converter. Only big problem is achieving lowest possible power supply noise for the trans-impedance converter.
 
Hi rolls,

You can have a dynamic range of 93db only and still a resolution power of 24bit, it means that the steps are finer, one step is 1 divide by 2 to the power of 24.
In other words, the binary word is not zero when it "leaves" noise

Full 144dB dynamic range (24-bits) is not required for practical playback unless you don't mind permanent hearing damage (jet engine at full blast produces approx. 140dB).

So the dynamic range has to be reduced to avoid too loud (peak) signals. Practical dynamic range is more like 50 ... 70dB.

Audio sets produce noise, and the weakest audible signal depends on noise level. Suppose the audio set has zero noise, the weakest audible sound would then be determined by human auditory system and ambient noise levels.

There is also the resolution limitation imposed by sample rate and timing jitter!

I attached an oscillogram of two 1 Khz sine waves, what signal do you think has highest bit depth?
 

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-ecdesigns- said:
Hi ccschua,

The TDA1541A appears to perform best with the trans-impedance converter. Only big problem is achieving lowest possible power supply noise for the trans-impedance converter.


I had a huge step forward after taking the pain to understand what is Idss, Vp (pinch off), BJT saturation/cut off and reverse /forward bias, common bass and source follower.

I found the problem with the transimpedance circuit using K117 GR series (with Idss limited to 6mA) and it is by changing the 'correct' resistor value, the problem was solved. I had also used -12V dc with pull down resistor to ensure the linearity region of K117 and to ensure K117 is not cut off by Idac=0 mA (giving Vds = 0) In the process, Drain or source they work the same (which I reverse and yet still got it work, OMG)

Now music is so real with the simple transimpedance. After going thru the thread on simple I/V conversion by Pedra Rodja, basically the simplified version by Jocko jive the circuit posted by ECDesigns.

I am about to try the charge transfer floating circuit soon and will report back what is the impression. Please let me know if any changes to the floating charge circuit.
 
-ecdesigns- said:
Hi rolls,
Full 144dB dynamic range (24-bits) is not required for practical playback unless you don't mind permanent hearing damage (jet engine at full blast produces approx. 140dB).
So the dynamic range has to be reduced to avoid too loud (peak) signals. Practical dynamic range is more like 50 ... 70dB.
Now you have missed up dynamic range and resolution power for the 3rd time, so I simply conclude, that you don't want to know it for obvious reasons.
Just for other readers: Dynamic range can be as low as 70db, but you maybe still hear the fine steps of a 24bit resolution. High resolution (24db) downloads are definitely a step in a new world and not recorded just for loud listening. Or the other way round: If you listen at moderate volume you may have just 50db (1:316) dynamic range. If this were the resolution, you would have less than 9bits (512steps), would be a strange experience.....
There are 24bit and even 32bit converters on the market. At least from a 24bit converter I can tell you that you can hear resolution very well, even at late night listening and even still fed with 16bit stuff. I love the TDA1541, and you have done wonderful things with it. I would have told you it is the best 2 years ago, but now..
I think the problem is that it behaves like a diva, you must try to tame it with surrounding components which produces new problems, a never ending story.
A new chip can have an area of 1 cm2, means shortest signal path, all its already there. I would be happy to see a finished TDA product for evaluation, because there are 2 TDA1541 S1 NOS (new old stock) chips waiting for a job, but in the meantime ..
I totally agree with you in one point: stay away from the mains. I even try to stay away from regulators. There is a benefit with new chips: I can feed them with batteries, they just need 3.3V, I need 4 of them for a chip, and that's it.
regards
Andre
 
Clock schematic

-ecdesigns- said:
Hi yygomez,



The oscillator runs on 5V (approx. 10mA), the 1.5V is used as reference voltage to bias the JFETs in the master clock.

The oscillator is basically a buffer with a phase shifter and a crystal filter in the feedback loop. This results in a pure, very low distortion 5Vpp sine wave at the amplifier input.

I already constructed a prototype with 8 crystals in the feedback loop (very difficult to tune), I now use simpler versions with 2 or 3 crystals that are less critical and more easy to build.

I picked the signal from the JFET input, using a second Buffer circuit.


I attached an oscillogram of a 2-crystal version running on a dirty 5V power supply and using a 1.5V alkaline reference voltage. I included the scope in the picture to verify settings. I used a 1:10 probe, and time base X10 setting. Frequency equals 11.2896 MHz.

The sine wave can be used to trigger a suitable high-speed comparator with high input impedance and low input capacity. but amplitude is also high enough to directly trigger connected loads (after unity gain buffering).


Hi John, where can we see the schematic of your clock so that we can build it and compare with other clocks?
 
I have been impressed with the simple transimpedance circuit and decided to make a board for it. I wonder what kind of cable should I use to bring the Rout and Lout from the TDA 1541a. The cable is about 5 in long and I have coaxial 75ohm shielded x 2 cable. Would this be a good choice or better to use shielded solid core.
 
Speaker attenuation experience

Having just stumbled upon this latter part of the thread I would like to add a couple of comments re attenuating the speaker output and bypassing the whole volume control thing.

I was amazed to find that this thread actually had information in it that to a great degree was similar to my current audio system pursuits so it is quite inspiring.

Currently I am nearing the completion of a nearly 4 year complete diy system project.. which includes digital and analogue playback. Nothing odd in that but the system is arranged so it can be configued in many ways, from the very direct to the very processed, active quad amping, different OB driver set ups etc.

Along the way I made several firm philosophical decisions about the system, one it had to be completely off the grid, two it had to be OB, three it had to be very efficient and four the amps were going to be my own version of gainclones (smd point to point).

Anyhow along the way I had lots of trouble with pots on the pre-amp, basically they seemed to effect sound quality way too much and I had real problems finding one that didn't detract too much.

A new problem cropped up when I finally got my OBs up and running, you see the main drivers and coax tweeters are around 100db efficient. maybe more with the OB effect, the problem was that I could not get the amp to run at anything like a clean level at anything like normal listening levels, but of course when turned up loud LOUD! all was peachy and clean.

Solution, put on some LPads and run the amp at a constant level below clipping.

The result, utterly wonderful, the dynamics, the clarity, everything was better and with the whole show on batteries the noise level nowhere to be noticed.

Ultimately I came the decision I needed and NOS dac on batteries, no pre-amp, a jfet buffer and gainclones feeding very high efficiency OBs for my digital front end playback. There are still issues I am trying to resolve but that will happen.

And now I find this thread talking about a similar concept, that SD player may just be the final link in the chain, I'm excited!

Anyhow the idea of speaker volume control works, regardless of what I thought might happen, it is a great solution, though a little less practical.
 
Clock circuit

-ecdesigns- said:

I use a different approach, it's basically a unity gain hybrid buffer, driving a tuned 3rd ... 12th order crystal filter through a phase shifter that includes an inductor. The crystal filter is loaded with correct impedance, and this signal is fed back to the input of the buffer. This way sine waves with very low distortion and high amplitude (approx. 9Vpp at the buffer input with 5V power supply) can be generated. This high amplitude is achieved by the inductor. The oscillator easily produces 4 ... 5Vpp at the buffer output.

This output signal was shaped to have relative fast positive going edge and slow negative going edge, in order to ensure accurate triggering by connected logic circuits (positive going edge), and minimizing interference by a slow negative going edge.

In order to minimize the effect of power supply noise, a battery reference voltage was used to bias the unity gain buffer (I now use a 3V lithium cell that will last as long as its shelf life).

In order to minimize the effect of varying capacitive loads, two separate discrete buffers were added to the oscillator. These buffers were designed for minimum frequency shift with varying load capacitance. In order to achieve lowest possible phase noise, I only connected one single clock load to each buffer.

This way very low phase noise could be achieved, and maintained, with connected loads and practical power supplies.

Hi John, Do you care posting a schematic of your clock?
BTW batteries can be noisy. There was an article on TNT audio showing that.
:angel:
 
Here is a Question regarding batteries;

Which of all the types, nicad, nimh, alkaline, lead acid, lithium are actually the cleanest when lightly loaded and not regulated?

I have seen reports that very large deep cycle batteries actually work for Dacs, perhaps they have the least noise under even very light loads?

I imagine a DAC is the most demanding of all audio uses in the low noise sense so there is probably some milage to gained here.
 
luxury54 said:


Hello ccschua,
can you post a simple schematic of what your final component values are?
i would give also a try with that same board as yours, thx !


An externally hosted image should be here but it was not working when we last tested it.


Select R2 to give Idac = 0mV.

Select R4 to give linearity of output.

Select R4- such that V source of T2 is about 0.7~1.0 V offset (from 9.0V during idle) (when Idac = 0)

R2 is around 4k.

R4 is around 2k7.

C1 is very important too.

special tks to ECDesign

your comment is welcome.