Re: Re: Re: Re: Re: Re: Miller compensation connection
My nit-picking? Is that supposed to be a joke? "Proper simulation"? Was my simulation improper? LOL.
You are missing the point. The "anomaly" outlined is repeatable with the same design (such as the one I provided) simulated in LTspice, Mcap or Multisim.
It doesn't matter that the absolute simulated THD values may vary by a significant degree, the THD is always higher with the miller cap connected to the "outer" connection.
It is a common misconception that shifting the miller cap to the first EF is a sure method to gain a little improvement in an amplfiers overall distortion performance, as the miller cap is removed as a load to the collector of the VAS and the miller loop gain is significantly increased.
Despite this, a linearity improvement that would seem to be commesurate with the reduced VAS loading and increased miller loop gain is seldom achieved and in some cases it can be shown that the amplifiers overall distortion performance is actually worsened.
That is significant and counter-intuitive, nu?
I'm not holding by breath for any of the geniuses here so above me to actually explain why this is so.
If one is refining (for example) a conventional Miller compensated-topology amplifier in which the slew rate is dictated by the LTP tail current and not the capacitive loading on the VAS, it would be a good idea to actually test the two feedback miller cap connections instead of just assuming that the performance would be better with the "outer" connection, right?
Bob Cordell said:
My nit-picking? Is that supposed to be a joke? "Proper simulation"? Was my simulation improper? LOL.
syn08 said:
You are missing the point. The "anomaly" outlined is repeatable with the same design (such as the one I provided) simulated in LTspice, Mcap or Multisim.
It doesn't matter that the absolute simulated THD values may vary by a significant degree, the THD is always higher with the miller cap connected to the "outer" connection.
It is a common misconception that shifting the miller cap to the first EF is a sure method to gain a little improvement in an amplfiers overall distortion performance, as the miller cap is removed as a load to the collector of the VAS and the miller loop gain is significantly increased.
Despite this, a linearity improvement that would seem to be commesurate with the reduced VAS loading and increased miller loop gain is seldom achieved and in some cases it can be shown that the amplifiers overall distortion performance is actually worsened.
That is significant and counter-intuitive, nu?
I'm not holding by breath for any of the geniuses here so above me to actually explain why this is so.
If one is refining (for example) a conventional Miller compensated-topology amplifier in which the slew rate is dictated by the LTP tail current and not the capacitive loading on the VAS, it would be a good idea to actually test the two feedback miller cap connections instead of just assuming that the performance would be better with the "outer" connection, right?
Re: Re: Re: Re: Re: Re: Re: Miller compensation connection
My point is precisely missing the point.
Here's my bottom line - I may not care about such "anomalies" before 1000% errors are understood and corrected. You first fix the infrastructure and then get into the "10%" details. Currently, to me, those 10% fall in the noise category.
G.Kleinschmidt said:
My point is precisely missing the point.
Here's my bottom line - I may not care about such "anomalies" before 1000% errors are understood and corrected. You first fix the infrastructure and then get into the "10%" details. Currently, to me, those 10% fall in the noise category.
syn08 said:
My 12W TMC amp simulated 8ppm THD-20. It measured ~10ppm THD-20. I wouldn't say that's a 1000% error.
1000%=botch-job
Bob's HEC amp has a measured THD20 of 6ppm and a simulated THD20 of 5.9ppm. Also in this case slightly less than an outrageous error of 1000%.
Bob's HEC amp has a measured THD20 of 6ppm and a simulated THD20 of 5.9ppm. Also in this case slightly less than an outrageous error of 1000%.
Hi Glen,
Could you tell us how exactly you simmed the "outer cap" compensation?
1. Just one cap tied to one of the emitters of the drivers (=wrong), or
2. Two caps, one tied to NPN emitter and the other one to the PNP emitter.
Cheers,
Edmond.
Could you tell us how exactly you simmed the "outer cap" compensation?
1. Just one cap tied to one of the emitters of the drivers (=wrong), or
2. Two caps, one tied to NPN emitter and the other one to the PNP emitter.
Cheers,
Edmond.
Re: 1000%=botch-job
Congratulations guys!
Of course, details like class A vs. class AB, bipolar vs. JFET models, consistent results vs. a lucky shot, etc... are not essential.
G.Kleinschmidt said:
Edmond Stuart said:Bob's HEC amp has a measured THD20 of 6ppm and a simulated THD20 of 5.9ppm. Also in this case slightly less than an outrageous error of 1000%.
Congratulations guys!
Of course, details like class A vs. class AB, bipolar vs. JFET models, consistent results vs. a lucky shot, etc... are not essential.
Edmond Stuart said:
I just tried a few things on the same design:
100pF miller comp cap connected to the VAS collector:
THD-20
0.011890% (the reference figure) 🙂
100pF miller comp cap connected to the NPN emitter:
THD-20
0.014297% 🙁
100pF miller comp cap connected to the PNP emitter:
THD-20
0.003204% 😕
Two parallel 50pF miller compensation caps, one connected to the NPN emitter, one to the PNP emitter:
THD-20
0.007942% 😎
The 100 ohm resistor bewteen the driver emitters split into two 50 ohm series resistors, with the a single 100pF miller comp cap connected to the junction:
THD-20
0.007941% (virtually identical to the last result) 😎
Cheers,
Glen
Re: Miller cap
Thanks Edmond.
The miller cap pick-off point is obviously sensitive to the non-linearity in the emitter followers, incurred by the base currents of the output devices. I guess this is further evidence that the "proper" sim of just a VAS by itself was pretty worthless.
No! wait, these comparative results all vary by less than an order of magnitude!
We clearly cannot draw any conclusions from this experiment whatsoever
😀
Cheers,
Glen
Edmond Stuart said:
Thanks Edmond.
The miller cap pick-off point is obviously sensitive to the non-linearity in the emitter followers, incurred by the base currents of the output devices. I guess this is further evidence that the "proper" sim of just a VAS by itself was pretty worthless.
No! wait, these comparative results all vary by less than an order of magnitude!
We clearly cannot draw any conclusions from this experiment whatsoever
😀
Cheers,
Glen
do you have a problem rounding log10?, your worst/best ratio would round up to "an order of magnitude"
obviously pursuing smaller improvements in a specific design can be sensible - but at some point the changes are too small and too specific to the exact circuit and measurement conditions to be cited as proving/disproving broad circuit design principles
and I did anticipate the load variation by adding a "disturbance rejection" measurement with an independent Isource loading on the ef output in my sims
obviously pursuing smaller improvements in a specific design can be sensible - but at some point the changes are too small and too specific to the exact circuit and measurement conditions to be cited as proving/disproving broad circuit design principles
and I did anticipate the load variation by adding a "disturbance rejection" measurement with an independent Isource loading on the ef output in my sims
G.Kleinschmidt said:
I just tried a few things on the same design:
100pF miller comp cap connected to the VAS collector:
THD-20
0.011890% (the reference figure) 🙂
100pF miller comp cap connected to the NPN emitter:
THD-20
0.014297% 🙁
100pF miller comp cap connected to the PNP emitter:
THD-20
0.003204% 😕
Two parallel 50pF miller compensation caps, one connected to the NPN emitter, one to the PNP emitter:
THD-20
0.007942% 😎
The 100 ohm resistor bewteen the driver emitters split into two 50 ohm series resistors, with the a single 100pF miller comp cap connected to the junction:
THD-20
0.007941% (virtually identical to the last result) 😎
Cheers,
Glen
These are worthwhile and interesting results, especially tapping from the PNP as opposed to the NPN driver.
However, I would expect less interesting results if the amplifier being simulated was using a Triple in the output stage. BTW, these appear to be very good THD-20 results for an amplifier that only uses a Double output stage.
Cheers,
Bob
Re: Re: Re: Re: Re: Miller compensation connection
Wasted?????
Read this: http://www.diyaudio.com/forums/showthread.php?postid=1504002#post1504002
Furthermore, I hope you'll realize that you have wasted my time buy not recognizing that an absolute error between simulation and real life has nothing to do (i.e. does not compromise) the correlation between the two of them.
jcx said:
Wasted?????
Read this: http://www.diyaudio.com/forums/showthread.php?postid=1504002#post1504002
Furthermore, I hope you'll realize that you have wasted my time buy not recognizing that an absolute error between simulation and real life has nothing to do (i.e. does not compromise) the correlation between the two of them.
Although I'm suspecting its a waste of my time I'll try again: nobody is debating the 10% effect. However, there's bigger fish to fry and before dealing with the finesses it should be much more useful (and, to me, interesting) if discrepancies like the one I got in my botch job would be addressed. Minor things like better device models, simulation tools calibration, matching simulations vs. experimental data (at least for certain classic topologies), etc...
Nothing sexy in this kind of work, I'm afraid...
Nothing sexy in this kind of work, I'm afraid...
syn08 said:
This is no different than demonstrating/knowing that picking off the nfb point on a PCB layout after the T-junction of the tracks joining the output-end of the emitter ballast resistors of the complementary output devices will result in slightly better distortion performance.
The little things all add up.
G.Kleinschmidt said:
An error found in the original HK Citation 12 amplifier, unless they
thought they would cancel some 2nd harmonic out.
variable take off point
Hi Glen,
You read my mind. 🙂
I have once suggested to implement a "variable take off point" in order to cancel the effects of induction from the (half wave rectified!) currents through the power supply leads or tracks. Of course, only applicable to class-B or AB. Perhaps you still remember it. If not, you can find it here:
Thread: Bob Cordell Interview: BJT vs. MOSFET
Page: 49
Post: 1207 and look at the pot P1 and the TMC network.
(for some reason, a direct link doesn't work)
Cheers,
Edmond.
G.Kleinschmidt said:
Hi Glen,
You read my mind. 🙂
I have once suggested to implement a "variable take off point" in order to cancel the effects of induction from the (half wave rectified!) currents through the power supply leads or tracks. Of course, only applicable to class-B or AB. Perhaps you still remember it. If not, you can find it here:
Thread: Bob Cordell Interview: BJT vs. MOSFET
Page: 49
Post: 1207 and look at the pot P1 and the TMC network.
(for some reason, a direct link doesn't work)
Cheers,
Edmond.
Re: variable take off point
Hi Edmond. Have you ever tried this is a real amp? If so, how sucessfull was it?
Cheers,
Glen
Edmond Stuart said:
Hi Edmond. Have you ever tried this is a real amp? If so, how sucessfull was it?
Cheers,
Glen
I would assume a start connection of th e emiiter balast resistors with the f/back take off point coming from the centre of the star also qualifies as a good practice?
Re: Re: variable take off point
Hi Glen,
Not yet. But when I start the PCB art work for my PMP amp, I'll make provisions for that little pot.
BTW, if it will work depends on which part of the amp is plagued most by these evil induction fields, but most likely it is the input stage. At this spot, the amplitude of the induced error increases linear with frequency (and its phase is shifted by +90 dgr.). Therefore, we need a cancellation thingie that acts via a capacitor[i/]. That's why I tied the pot to the TMC network.
The cancellation principle is so basic and simple, that I don't see why it shouldn't work. I know there are also some second order effects, but as they are much smaller it is not worth the effort to trim them also out.
Cheers,
Edmond.
G.Kleinschmidt said:
Hi Glen,
Not yet. But when I start the PCB art work for my PMP amp, I'll make provisions for that little pot.
BTW, if it will work depends on which part of the amp is plagued most by these evil induction fields, but most likely it is the input stage. At this spot, the amplitude of the induced error increases linear with frequency (and its phase is shifted by +90 dgr.). Therefore, we need a cancellation thingie that acts via a capacitor[i/]. That's why I tied the pot to the TMC network.
The cancellation principle is so basic and simple, that I don't see why it shouldn't work. I know there are also some second order effects, but as they are much smaller it is not worth the effort to trim them also out.
Cheers,
Edmond.