Ian,
in my opinion the FPGA should do the "dirty" job only, so I believe that the clock division should be kept far from it, even with a pair of synchronous counters.
This is what we have done in our FIFO Lite isolating the return to the FPGA via optocouplers (even the master clock is optically isolated).
Maybe I'm wrong but will see the measurement result soon.
The regenerative divider remains the only option to get the best result, we expect better close in phase noise performance of the divided clock against the master clock, since theoretically the division improves the phase noise.
IMHO the FPGA should be slaved to the crucial clock for the DAC, so the BCK or the LRCK depending on the DAC, because the crucial signal should feed directly the DAC (master clock divided by n) without crossing the FPGA.
We have choosen the LRCK because our new discrete DACs switch on the LRCK.
DACs operating on the master clock don't need a FIFO, just keep the master clock as clean as possible, so using a USB to I2S converter based on a low noise oscillator should be enough.
Digital electronics in the end always comes back to analog issues.
in my opinion the FPGA should do the "dirty" job only, so I believe that the clock division should be kept far from it, even with a pair of synchronous counters.
This is what we have done in our FIFO Lite isolating the return to the FPGA via optocouplers (even the master clock is optically isolated).
Maybe I'm wrong but will see the measurement result soon.
The regenerative divider remains the only option to get the best result, we expect better close in phase noise performance of the divided clock against the master clock, since theoretically the division improves the phase noise.
IMHO the FPGA should be slaved to the crucial clock for the DAC, so the BCK or the LRCK depending on the DAC, because the crucial signal should feed directly the DAC (master clock divided by n) without crossing the FPGA.
We have choosen the LRCK because our new discrete DACs switch on the LRCK.
DACs operating on the master clock don't need a FIFO, just keep the master clock as clean as possible, so using a USB to I2S converter based on a low noise oscillator should be enough.
Digital electronics in the end always comes back to analog issues.
I wander how dividers at outputs of dedicated clock circuits (LMK03806, SI5340) fare in this respect...
@phofman
They are all PLL based so the close-in phase noise would be expected bigger.
LMK03806 could be better than SI5340 according to the specifications.
Regards,
Ian
They are all PLL based so the close-in phase noise would be expected bigger.
LMK03806 could be better than SI5340 according to the specifications.
Regards,
Ian
Thanks. I was specifically aiming at performance of the output dividers which you are discussing here.
Thanks phofman, didn't see any mention on how they made the dividers. I'll look into it.
Ian
Ian
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What is the difference between the FifoPi first and third version please ?
Were there layouts changes or also passive & active parts as well ? Can one trweak the first version towards a third version like (aproximativly) ?
Were there layouts changes or also passive & active parts as well ? Can one trweak the first version towards a third version like (aproximativly) ?
What's new in Q3 version
This Q3 version of FiFoPi, a direct improvement of FiFoPi Q2, benefits from several enhancements that increase the performance of the module in order to offer you a sound reproduction of ever higher quality.
• Supports oscillators (XO) with and without OE pin.
• Uses 3.3V for a clean DC power supply. All LDOs have been removed to allow direct operation with a better 3.3V power solution via LifePO4 or ultra-capacitor.
• Optional U.FL input for connection to an external oscillator via coaxial cable.
• Supports XO (oscillator) Single Mode.
• XO oscillator support in SMT format for easy replacement.
• Isolated MUTE and DSD EN outputs for better operation with pure DSD DACs or external PCM/DSD DACs (via TransportPi or HdmiPi).
• New high-speed 300MHz flip-flops to reduce the additional jitter of the final I2S/DSD reclocking.
• Optimized decoupling networks to improve power supply performance.
IAN CANADA FIFOPI Q3 ULTIMATE FIFO Reclocker Module PCM 32bit 768kHz DSD1024 DoP - Audiophonics
Ian Canada's FiFoPi Ultimate has been designed to significantly reduce the jitter of the digital audio signal produced by a Raspberry Pi, before it can be transmitted back to your DAC. To do this, the module follows a 3-step process:
Buffering and reclocking of the digital audio signal using clocks (46.1520MHz and 45.1584MHz) and low jitter logic components. This step makes it possible not to depend on the non audio-dedicated clock of the Raspberry Pi. which generates jitter to work. Indeed, the Raspberry Pi's clock must perform a non-integer division to be able to convert its operating frequency to a clock frequency related to the audio. The clocks on the FiFoPi module are mounted on a stand and can therefore easily be replaced by even better models.
The FiFoPi uses built-in galvanic isolation to isolate the reclocking process and your DAC from the noise generated by the data processing performed by your Raspberry Pi due to the use of a DC-DC converter.
The use of a high-quality power supply separate from the Raspberry Pi (sold separately) for the reclocking process and clocks allows the FiFoPi to produce a very low jitter digital audio stream. Just as you can choose the quality of the clocks, you can select the power supply of your choice.
The module is Raspberry Pi HAT compatible, allowing an extremely simple integration. It supports PCM I2S up to 768kHz, native DSD up to DSD1024 and integrates a DoP decoder allowing the reading of the DSD from a PCM I2S signal provided by the GPIO of the Raspberry Pi. A 16bit PCM I2S to 32bit lossless converter allows the FiFoPi to work with DACs that do not support 16bit PCM I2S formats. The module also incorporates two isolated power inputs to provide clean power to both the FiFoPi and Raspberry Pi with the presence of an isolated GPIO connector.
The delivered FiFoPi Q3 is an updated version of the FiFoPi S2, benefiting from improvements to optimize signal quality.
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You can see it on the board written under the word ultimate.
I have the first edition, on the Audiophonics site the Q2 version is shown on the Q3 order field.
See pictures.
@Ian, on the Audiophonics website they announce the Q3 version will be available on 16 sept. Is this correct?
I have the first edition, on the Audiophonics site the Q2 version is shown on the Q3 order field.
See pictures.
@Ian, on the Audiophonics website they announce the Q3 version will be available on 16 sept. Is this correct?
Attachments
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You can see it on the board written under the word ultimate.
I have the first edition, on the Audiophonics site the Q2 version is shown on the Q3 order field.
See pictures.
@Ian, on the Audiophonics website they announce the Q3 version will be available on 16 sept. Is this correct?
@Supersurfer
FifoPi Q3 are under production. Hopefully they will be available in next week.
Regards,
Ian
StationPi PCB
StationPi PCB
1. Two stacks configuration. Before FifoPi is the digital stack. After FifoPi is the audio stack.
2. Double ground shielding walls, four shield layers in total
3. Power GPIO directly
4. Great to build DAC or digital transport

StationPi_PCB by Ian, on Flickr

StationPi_FifoPi_TransportPi by Ian, on Flickr
Ian
StationPi PCB
1. Two stacks configuration. Before FifoPi is the digital stack. After FifoPi is the audio stack.
2. Double ground shielding walls, four shield layers in total
3. Power GPIO directly
4. Great to build DAC or digital transport

StationPi_PCB by Ian, on Flickr

StationPi_FifoPi_TransportPi by Ian, on Flickr
Ian
^^ Nice timing on the StationPi post.
I just put in an order for an RPi Compute3+ and some GPIO Ribbon Extenders to try to tackle a similar issue.
Trying to cancel order before business hours in the morning...
The StationPi is a more elegant solution and I can move on to RPi4.
I just put in an order for an RPi Compute3+ and some GPIO Ribbon Extenders to try to tackle a similar issue.
Trying to cancel order before business hours in the morning...
The StationPi is a more elegant solution and I can move on to RPi4.
Its great idea, I was thinking abuot it for ages, even was planning to make it myself. The only my concern is that Pi is mounted upside down and by using Pi 4 it will be heat issue.
Would RPi4 be OK with the sink facing downward?
What the height of the heat sink? I can also open a window if it is too high.
Any other thought?
Regards,
Ian
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