Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter

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wlowes

wlowes

Member
Joined 2007
ReclockPi

If I understand correctly, those of us with DACs that trigger off LRCK such as my TDA1541a have been interested in an alternate FIFO implementation from Andrea Mori that claims a value proposition that it's LRCK bypasses FPGA and it is as clean as the clock wrt jitter.

Taking that solution would require replacing the investment made in FIFOPi for an alternate multi PCB solution requiring $ and re implementation of chassis to accommodate a different architecture.

I believe you are advocating that the addition of ReclockPi achieves a similar result by building on the FIFOPi stack.

Two questions...
1. Is this a fair summary of ReclockPi value proposition wrt existing FIFOPi users with LRCK triggered DAC?
2. What is the anticipated price and availability of ReclockPi?
Thanks :)
 
iancanada

iancanada

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Joined 2009
twitter.com/iancanadaTT
Paid Member
@Markw4

Master clock mode is OK, but only good for simple ESS DACs. Master clock mode is impossible to make a great DAC because of the so many limitations.

1. Master mode will never support native DSD format.
2. It is impossible to support any S/PDIF input using the master clock mode.
3. Master mode doesn't take music from any USB streamer.
4. Master mode doesn't take music from any HDMI/I2S input.
4. Master mode DAC can only work with a single RPi or BBB as input. There is no way to expand functions.

And even more, additional EMI noise will be expected inside the ESS DAC once the internal master clock generation logic is enabled, which will degrade the sound quality. We also can not guarantee that the internal master LRCK and SCK are in the same high quality level as those generated by a ReClockPi's discrete components.
Click to expand...

@Markw4
Very good comments.

1. I had master mode working with DSD
That's not a native DSD, just DoP from RPi in a I2S package.

2. Master mode only applies to I2S, not SPDIF.
Yes, that's one of the limitations of the master mode.

3. Don't see why master mode should not be able to work fine with a FIFO.
Master mode can not work with any other input except a RPi, that's another limitation of master mode.

3. Allo uses master mode with RPi.
It's true. But can only work with a PRi.

Regards,
Ian
 
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iancanada

iancanada

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Joined 2009
twitter.com/iancanadaTT
Paid Member
wlowes said:
If I understand correctly, those of us with DACs that trigger off LRCK such as my TDA1541a have been interested in an alternate FIFO implementation from Andrea Mori that claims a value proposition that it's LRCK bypasses FPGA and it is as clean as the clock wrt jitter.

Taking that solution would require replacing the investment made in FIFOPi for an alternate multi PCB solution requiring $ and re implementation of chassis to accommodate a different architecture.

I believe you are advocating that the addition of ReclockPi achieves a similar result by building on the FIFOPi stack.

Two questions...
1. Is this a fair summary of ReclockPi value proposition wrt existing FIFOPi users with LRCK triggered DAC?
2. What is the anticipated price and availability of ReclockPi?
Thanks :)
Click to expand...

Thanks wlowes,

I'll post more measurement results so that you can figure it out by yourself by analyzing the results.

Andrea Mori also did a good job. It would be better for you to have both to see which one will be more suitable for you.

Regards,
Ian
 
D

Deleted member 537459

I have a question, in about 1 year we reached fifopi Q3, and the improvements have not been huge. you talk about ultimate and now you come out with a "real" reclock ... maybe I missed something, the fifopi utimate was not supposed to be the top over the top? also Ian you haven't explained very well why a discrete component reclock is needed after a "reclock". maybe the fifopi is not a reclock? I'm confused. another question, because everything is always stacked and continues to bring noise throughout the chain

as you well know mine is not a controversy, thank you for your contribution to the audiophile world and you know, that I bought you a lot of material from you and audiophonics. mine is just to have a more concrete clarification. thank you and greetings

Gavroche
 
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dddac

dddac

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Joined 2003
blog.dddac.com
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iancanada said:
Both ReClockPi LRCK jitter and SCK jitter are also reduced to a best possible level when upgrading with it. The ReClockPi’s low jitter performance benefits from its discrete low noise secondary re-clock logic that is first time introduced to my gears.

Please find the attached time jitter testing results I did yesterday for the improvement before and after a ReClockPi.

When playing a 88.2KHz music, the FifoPi Q3 LRCK RMS jitter was 7.42 ps. After a ReClockPi installed, the same LRCK RMS jitter had been reduced to 6.17 ps. That’s a pretty big improvement to the signals that are already in very good quality. It would be great news for thoseDACs that are sensitive to the I2S/DSD jitter, such as ESS DACs, TDA1541 DACs, DDDAC and many others.

https://flic.kr/p/2kUhuBp
LRck88JitterBeforeAfterReClockPi by Ian, on Flickr

Ian
Click to expand...

Can you do the same for BCK Ian? For the DDDAC that is the important one, not LRCK
 
G

gionag

Member
Joined 2007
Hi Ian,

I have a question on the McDualXO.
I have found that the clock signal that goes back to the FIFO (the one that exits from the u.fl FIFO MCK / TO FIFO), pass trough two inverters.

My limited knowledge push me thinking that is some form of re-alignment, something needed for proper working of the fifo with the reclock stage.

I am asking because i am thinking to swap for another clock selector / reclock board for the FIFO (a possibility that yourself claimed feasible in the manual) and i want to be sure if that is a feature needed for the correct working.

thanks
 
A

A123

Disabled Account
Joined 2020
+3

Of course I am in for the RCP, but don't know the timing as I'm focused now on a PC Build.

I just love that it's low profile to fit into my portable Q3 without adding too much heft. This also has the benefit of leaving the door wide open for Pulsar-like clocks. It would be an amazing portable transport if I can scale up to Pulsar-like clocks one day. The ShieldPi (needs AUX GPIO extender) adds too much height for portable use, thus Pulsar-like clocks not an portable option. I do need that gap opening to fit in those clocks.

I ended up splitting my project into two. Portable Q3 since I got it working again, but in a more compact way. And a 12V low latency realtime kernel i9 PC Build.

For the PC Build, I will use Ian's MKIII to power but unsure if I will add anything else because I'm going the PCIe USB route.

usb-bridge.jpg


If Ian can develop a USB PCIe with clock-rolling abilities, I would seriously consider that route. As of now, I'm not sure a BridgePi Q3 RPI-less route addon is the way to go with this PC build. Although I have the SuperCaps infrastructure in place. I'm not sure if adding anything extra will cause more harm than good since my DAC doesn't really need a clock for the USB side. For the toslink side, it's necessary IMO.

If Taiko Audio releases a PCIe USB, then that changes things:

SGM Extreme Music Server – Taiko Audio
 
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iancanada

iancanada

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Joined 2009
twitter.com/iancanadaTT
Paid Member
ReClockPi LRCK waveform and phase noise plot

I have never seen such a perfect LRCK waveform before I developed my ReClockPi.

It’s almost an ideal square wave. Rising/falling time only 0.9ns. Rising/Falling edges are super clean. No any ripples on both high and low logic levels. That ensures the lowest possible EMI noise will be transferred into the DAC along with the LRCK signal. It’s the newly designed discrete logic circuits that results in this low noise re-clock performance.

Any applications that rely on the LRCK for sound quality will benefit a lot from this ReClockPi. Please find the first picture for the measurement result I did today.

Testing conditions:
8GS/s sampling
1GHz Global bandwidth
50 ohm DC coupling
0.1us/div time base

When converting the RMS jitter into phase noise, the LRCK phase noise plot is also very promising. Though in the real world, it’s impossible to get -6dB improvement at each time divided by 2, but this RcClockPi 88.2 KHz LRCK phase noise plot could be the best one I have ever seen. When replacing the CCHD957 MCLK with a better XO, there will be still more room for a new improvement. Please see the second picture for this calculated phase noise plot. Please note that the integration bandwidth was wide from 0.1Hz to 1MHz.

An externally hosted image should be here but it was not working when we last tested it.

LRck88WaveformReClockPi by Ian, on Flickr

An externally hosted image should be here but it was not working when we last tested it.

LRCKphaseNoise by Ian, on Flickr

Ian
 
A

alecm

Member
Joined 2011
iancanada said:
Both ReClockPi LRCK jitter and SCK jitter are also reduced to a best possible level when upgrading with it. The ReClockPi’s low jitter performance benefits from its discrete low noise secondary re-clock logic that is first time introduced to my gears.

Please find the attached time jitter testing results I did yesterday for the improvement before and after a ReClockPi.

When playing a 88.2KHz music, the FifoPi Q3 LRCK RMS jitter was 7.42 ps. After a ReClockPi installed, the same LRCK RMS jitter had been reduced to 6.17 ps. That’s a pretty big improvement to the signals that are already in very good quality. It would be great news for thoseDACs that are sensitive to the I2S/DSD jitter, such as ESS DACs, TDA1541 DACs, DDDAC and many others.

https://flic.kr/p/2kUhuBp
LRck88JitterBeforeAfterReClockPi by Ian, on Flickr

Ian
Click to expand...

Hi Ian,

Promising results! if the effect is cumulative, can two reclockpi be used in a row?
 
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