ReClockPi
ReClockPi was designed to upgrade the performance of the FifoPi to a higher possible level. It could be the only solution so far that can improve the I2S/DSD signal quality of a FifoPi even more.
Basically a ReClockPi has two things:
1. An ultra low noise low jitter secondary re-clock stage.
2. A ShieldPi (Uses the top layer of the multi-layers PCB as the shield layer).
ReclockPi uses high speed discrete logic chips to deal with IR-drop issues of the multi-bit flip-flop/counter re-clock logic in order to lower the signal noise and to reduce the clock jitter even more . It really makes a difference. After upgrading a Fifopi with a ReClockPi, the I2S/DSD signal quality has been reached to an incredible level.
The real measurement results were very promising. And the listening test gave me even more surprise.
Please take a look at the attached test waveform of a 88.2KHz LRCK signal from a FifoPi and the same signal after a ReclockPi. My digital oscilloscope was running at 4GS/s sampling with 1GHz signal bandwidth.
More updates will be posted soon.
LRck88SignalBeforeAfterReClockPi by Ian, on Flickr
ReclockPi1 by Ian, on Flickr
Ian
ReClockPi was designed to upgrade the performance of the FifoPi to a higher possible level. It could be the only solution so far that can improve the I2S/DSD signal quality of a FifoPi even more.
Basically a ReClockPi has two things:
1. An ultra low noise low jitter secondary re-clock stage.
2. A ShieldPi (Uses the top layer of the multi-layers PCB as the shield layer).
ReclockPi uses high speed discrete logic chips to deal with IR-drop issues of the multi-bit flip-flop/counter re-clock logic in order to lower the signal noise and to reduce the clock jitter even more . It really makes a difference. After upgrading a Fifopi with a ReClockPi, the I2S/DSD signal quality has been reached to an incredible level.
The real measurement results were very promising. And the listening test gave me even more surprise.
Please take a look at the attached test waveform of a 88.2KHz LRCK signal from a FifoPi and the same signal after a ReclockPi. My digital oscilloscope was running at 4GS/s sampling with 1GHz signal bandwidth.
More updates will be posted soon.
LRck88SignalBeforeAfterReClockPi by Ian, on Flickr
ReclockPi1 by Ian, on Flickr
Ian
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Hi Ian,
I would also like to order ReClockPi!
Another two questions regarding HDMIpi Receiver:
- Can you please help me with the Specs of L4? I took it off but want to put it back on to make the HDMIpi powered through the HDMI cable again
- and do you know if the HDMI cable provides enough power to also power (besides HDMIpi receiver) the isolated side of an I2S isolator IC such as the IL715?
Thanks!
I would also like to order ReClockPi!
Another two questions regarding HDMIpi Receiver:
- Can you please help me with the Specs of L4? I took it off but want to put it back on to make the HDMIpi powered through the HDMI cable again
- and do you know if the HDMI cable provides enough power to also power (besides HDMIpi receiver) the isolated side of an I2S isolator IC such as the IL715?
Thanks!
How to upgrade a FifoPi with a ReClockPi
Please see the attached picture for how to upgrade a FifoPi with a ReClockPi.
Only need one u.fl cable to connect MCLK signal from FifoPi to ReclockPi. That's very simple.
By default, FifoPi shares the clean side 3.3V with ReClockPi. But can be upgraded to separated 3.3V power supplies at any time.
BTW, under the FifoPi is a RaspberryPi Zero (without WIFI). Less than $10-. Doing a good job. I like it.
ReclockPiFifoPi by Ian, on Flickr
Ian
Please see the attached picture for how to upgrade a FifoPi with a ReClockPi.
Only need one u.fl cable to connect MCLK signal from FifoPi to ReclockPi. That's very simple.
By default, FifoPi shares the clean side 3.3V with ReClockPi. But can be upgraded to separated 3.3V power supplies at any time.
BTW, under the FifoPi is a RaspberryPi Zero (without WIFI). Less than $10-. Doing a good job. I like it.
ReclockPiFifoPi by Ian, on Flickr
Ian
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I confess, that I do not understand how ReclockPi works. I get that it acts as another shield to EMI/RF radiation. But if FifoPi puts out an LRCK with some level of jitter, how does ReclockPi improve it? The name reclock implies reclocking the output of FIFO, but I do not see a clock input? Again, I am just not following the concept. Is it bypassing the LRCK signal generated by FIFOPi FPGA and instead generating it using a hi speed switch from the clock signal?
@wlowes
@nounouchet
FIFO buffer and re-clock are two different things.
FIFO buffer uses buffer memory to replace the digital music stream with a brand new timing which generated by a new low jitter new (FIFO works as a clock timing isolator between two clock domains).
Re-clock makes I2S/DSD output signal re-align the the new MCLK to reduce the I2S/DSD jitter.
FifoPi has a built in re-clock stage. We can call it the first re-clock stage.
ReClockPi is a low noise low jitter secondary re-clock stage. By upgrading a FifoPi with a ReClockPi, the I2S/DSD signal quality (both noise and jitter) can be improved even more thus better sound quality will be expected.
To achieve the best possible low noise and low jitter performance, ReClockPi was implemented by all discrete logic chips. It has around 150 tiny SMT components on a four layers double side mounting PCB. It could be almost impossible to include the ReClockPi into a FifoPi because of the limitation of the size of the PCB. And even more, ReClockPi has ShiledPi function. So, the current independent configuration can reduce the EMI noise even more.
I have been using a prototype ReClockPi in my own system for more than two months. I listen to music with it everyday. I'm really happy with it.
Here is my system:
The Best Sound Quality Audiophile DIY DAC I Built in 2020 - YouTube
I'll have more details to post soon.
Regards,
Ian
@nounouchet
FIFO buffer and re-clock are two different things.
FIFO buffer uses buffer memory to replace the digital music stream with a brand new timing which generated by a new low jitter new (FIFO works as a clock timing isolator between two clock domains).
Re-clock makes I2S/DSD output signal re-align the the new MCLK to reduce the I2S/DSD jitter.
FifoPi has a built in re-clock stage. We can call it the first re-clock stage.
ReClockPi is a low noise low jitter secondary re-clock stage. By upgrading a FifoPi with a ReClockPi, the I2S/DSD signal quality (both noise and jitter) can be improved even more thus better sound quality will be expected.
To achieve the best possible low noise and low jitter performance, ReClockPi was implemented by all discrete logic chips. It has around 150 tiny SMT components on a four layers double side mounting PCB. It could be almost impossible to include the ReClockPi into a FifoPi because of the limitation of the size of the PCB. And even more, ReClockPi has ShiledPi function. So, the current independent configuration can reduce the EMI noise even more.
I have been using a prototype ReClockPi in my own system for more than two months. I listen to music with it everyday. I'm really happy with it.
Here is my system:
The Best Sound Quality Audiophile DIY DAC I Built in 2020 - YouTube
I'll have more details to post soon.
Regards,
Ian
Last edited:
ReClockPi jitter
Both ReClockPi LRCK jitter and SCK jitter are also reduced to a best possible level when upgrading with it. The ReClockPi’s low jitter performance benefits from its discrete low noise secondary re-clock logic that is first time introduced to my gears.
Please find the attached time jitter testing results I did yesterday for the improvement before and after a ReClockPi.
When playing a 88.2KHz music, the FifoPi Q3 LRCK RMS jitter was 7.42 ps. After a ReClockPi installed, the same LRCK RMS jitter had been reduced to 6.17 ps. That’s a pretty big improvement to the signals that are already in very good quality. It would be great news for thoseDACs that are sensitive to the I2S/DSD jitter, such as ESS DACs, TDA1541 DACs, DDDAC and many others.
LRck88JitterBeforeAfterReClockPi by Ian, on Flickr
Ian
Both ReClockPi LRCK jitter and SCK jitter are also reduced to a best possible level when upgrading with it. The ReClockPi’s low jitter performance benefits from its discrete low noise secondary re-clock logic that is first time introduced to my gears.
Please find the attached time jitter testing results I did yesterday for the improvement before and after a ReClockPi.
When playing a 88.2KHz music, the FifoPi Q3 LRCK RMS jitter was 7.42 ps. After a ReClockPi installed, the same LRCK RMS jitter had been reduced to 6.17 ps. That’s a pretty big improvement to the signals that are already in very good quality. It would be great news for thoseDACs that are sensitive to the I2S/DSD jitter, such as ESS DACs, TDA1541 DACs, DDDAC and many others.
LRck88JitterBeforeAfterReClockPi by Ian, on Flickr
Ian
@Markw4
Master clock mode is OK, but only good for simple ESS DACs. Master clock mode is impossible to make a great DAC because of the so many limitations.
1. Master mode will never support native DSD format.
2. It is impossible to support any S/PDIF input using the master clock mode.
3. Master mode doesn't take music from any USB streamer.
4. Master mode doesn't take music from any HDMI/I2S input.
4. Master mode DAC can only work with a single RPi or BBB as input. There is no way to expand functions.
And even more, additional EMI noise will be expected inside the ESS DAC once the internal master clock generation logic is enabled, which will degrade the sound quality. We also can not guarantee that the internal master LRCK and SCK are in the same high quality level as those generated by a ReClockPi's discrete components.
It's just a discussion
Regards,
Ian
Master clock mode is OK, but only good for simple ESS DACs. Master clock mode is impossible to make a great DAC because of the so many limitations.
1. Master mode will never support native DSD format.
2. It is impossible to support any S/PDIF input using the master clock mode.
3. Master mode doesn't take music from any USB streamer.
4. Master mode doesn't take music from any HDMI/I2S input.
4. Master mode DAC can only work with a single RPi or BBB as input. There is no way to expand functions.
And even more, additional EMI noise will be expected inside the ESS DAC once the internal master clock generation logic is enabled, which will degrade the sound quality. We also can not guarantee that the internal master LRCK and SCK are in the same high quality level as those generated by a ReClockPi's discrete components.
It's just a discussion
Regards,
Ian
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