Assemblage Power Amp

Well, they just take apart the CFB on the othere thread, poor Ricardo.
 

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hehe... nevertheless the nobrainer works quite well 🙂

🙂 That's how it goes, we do not expect to build the 'final answer to OPS, VAS and INP' in one go. That needs a bit more work. The intermediate results are needed to learn from and to evaluate. Choices are wrong or good, that does not matter as long as we try for excellence and bring each experiment to a conclusive (note: not successful) end, we are doing good.

https://www.youtube.com/watch?feature=player_detailpage&v=aboZctrHfK8
 
While waiting for the boards I have been playing with simulations using MJL3281 and MJL1302 for the output..... needed to reset the vbias value and it sims ok but somehow it looks much more sensitive to miller cap and distortion also higher when input is over 1v.
 

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Frans, when you lower the internal gain in the way you are doing you should put the 0.22 resistors in the emitters of the power transistors not in the collector , and you have to lower the emitter and collector resistors of the driver transistors , use 22 ohms for both like Ricardo is using.
 
Frans, when you lower the internal gain in the way you are doing you should put the 0.22 resistors in the emitters of the power transistors not in the collector , and you have to lower the emitter and collector resistors of the driver transistors , use 22 ohms for both like Ricardo is using.

Sergio, yes I know, but this is not what I am using, it was done to show the effect of these in simulation, and to provoke discussion (as is working). I'm not building this, or the JG amp, I'm just poking a bit and helping to keep the ideas going. As I just discussed this with Joachim, I noted that it would be a good idea if other people put there idea's in simulations and show us there results, so... make it so 🙂

https://www.youtube.com/watch?feature=player_detailpage&v=X6oUz1v17Uo
 
Well, they just take apart the CFB on the othere thread, poor Ricardo.

Hope that this will clear things a bit 🙂.

The output stage that Ricardo uses is not a CFP stage, it does not have the high internal gain that CFP stages have, it does not have the same thermal feedback that a CFP stage have, it does not behave like a CFP in the crossover point.
It resembles much more with a EF stage but with even less gain than a EF stage, all the comments about CFP stages that was made in the Douglas Self thread are true, but they not fit in here.
 
While waiting for the boards I have been playing with simulations using MJL3281 and MJL1302 for the output..... needed to reset the vbias value and it sims ok but somehow it looks much more sensitive to miller cap and distortion also higher when input is over 1v.

Ricardo, there are some problems that you need to address in your design. The most important is that you can not use the BC327/337 in those positions you have to use bjt with at least 80Vce, the 2sc2240 will work but have different pin position than the bc327/337.

Other is that the open loop phase margin is only 40º, that is due to the R30, R31, you need to shunt this resistors with a capacitor (at least 100n)
 
This is the EF vs Ricardo output stage (ROS for short 🙂 ).
The second image the emitter resistors of the EF have to be increase to 0.6 for matching the ROS gain, the ROS have a lower gain than the EF because is driven by a higher impedance , in terms of thermal control I think that ROS and EF may be very similar, the ROS may be more thermal stable and emitter resistors can be even lower than 0.2 for lower crossover distortion, I think that even a 0.1R will work here, but is need further testing.
Like the EF stage, in ROS also all the output, drivers and bias spreader transistors must be mounting in the same heat-sink for thermal control ..
 

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