The circuit ceases operating as a negative feedback control system, and instead becomes a positive feedback oscillator, when phase shift increases from 180 degrees to 360 degrees. On the LTSPICE open loop gain plots, that phase crossover frequency is
AND it is observed that jacking around with the compensation components of the feedback control system has no effect upon the ringing frequency.
AND it is observed that the output transistor's gm has no effect upon the ringing frequency {high gm when Iout steps from 0 to 1.5A ; low gm when Iout steps from 1.5A to 0}
- 20 MHz in post #417
- 35 MHz in post #479
- 55 MHz in post #486
- 50 MHz in post #492
AND it is observed that jacking around with the compensation components of the feedback control system has no effect upon the ringing frequency.
AND it is observed that the output transistor's gm has no effect upon the ringing frequency {high gm when Iout steps from 0 to 1.5A ; low gm when Iout steps from 1.5A to 0}
A possible ringing (not actual, hard oscillations) occurs at the frequency where the loop gain crosses unity. Depending upon the phase margin remaining at that frequency, there will be more or less damped oscillations, or over-critical damping. What happens at other frequencies might cause fringe oscillations, but the ringing will find its cause there (it could also result in hard, sustained oscillations, but only if the phase margin becomes <0, which should normally be easily spotted [what happens at really high frequencies, like tens of MHz for this kind of LF setup is complete conjecture, unless you have real, measured data to enter into the sim]).
Here, based on this sim, the UGF seems to be around 500KHz average, with a phase margin that should not result in such a ringing, but for an open-ended sim based on purely theoretical values, a 0.5 factor on the UGF and ~90° uncertainty on the phase margin is not especially shocking.
That's in the right ballpark anyway.
That said, I am not sure at all that the root cause lies there: it is just a plausible lead.
Agreed: that's the most disturbing symptom here
Ditto
But we have to find an explanation...
If a supply is measured correctly, it should stay well under-damped for any frequency (OK, maybe >150MHz begins to be overkill, but I am not even 100% sure about that), and such a ringing, if it is real and not an artifact of the measurement method means that there is a large impedance peak at ~225KHz.
This is in a range that is completely unhealthy, because the PSRR of amplifiers, opamps, ... begins to degrade in that range of frequency.
Anyway, it is not really difficult to achieve a good impedance curve for these frequencies: you need to balance the impedances of the active circuits (mainly inductive) and that of the bypasses (capacitive) in a way that doesn't result in a too high synthetic Q. That could mean some bypass caps damped by a small series resistance, or active circuits compensated in a softer manner, or both, but it is achievable, and should be achieved.
Of course, when you seek very high performance, with a very low impedance up to very high frequencies things become more complicated, but when faced to the dilemma, you have to kill the performance at most of the frequencies in order to avoid a single nasty peak.
I always feel like Mark has the answer all along and is just waiting for numb nuts like me to catch up. 
It did seem to me that it could not be a loop gain/phase margin issue (frequency too low and changes to compensation didn't make a difference). But it did seem to me that it was a real artefact either of the reg board or the test setup i.e. that one can't just ignore it and it is a problem that needed fixing.
My emphasis. But any damped RLC resonance dies out over time depending on the level of resistance / damping factor. So perhaps your last sentence is much more pertinent.
How do you determine that the circa 215kHz is in proportion to dI/dT when current isn't being measured? dI = 1.5. dT? I guess you look at the data sheets for the components switching the load on-off. 30ns fall time for the MCP1407, turn off delay time for the STP27N3 of 13ns followed by fall time of 2.8ns....?? I'm missing something (a lot) in the maths.
It did seem to me that it could not be a loop gain/phase margin issue (frequency too low and changes to compensation didn't make a difference). But it did seem to me that it was a real artefact either of the reg board or the test setup i.e. that one can't just ignore it and it is a problem that needed fixing.
My emphasis. But any damped RLC resonance dies out over time depending on the level of resistance / damping factor. So perhaps your last sentence is much more pertinent.
How do you determine that the circa 215kHz is in proportion to dI/dT when current isn't being measured? dI = 1.5. dT? I guess you look at the data sheets for the components switching the load on-off. 30ns fall time for the MCP1407, turn off delay time for the STP27N3 of 13ns followed by fall time of 2.8ns....?? I'm missing something (a lot) in the maths.
The young Boy Scout who is trying to earn his Circuit Design merit badge, is the one whose job is to gradually accumulate a solution. Asking the Review Committee "okay so what's the right answer, I'm tired of this" is not how you earn the merit badge.
Similarly, for the Review Committee, "Help me Obi Wan Kenobi, you're my only hope!" should be mostly ignored, not heeded; it is not how you guide young Padawan Learners* towards becoming circuit designers.
* Jedis in training.
Similarly, for the Review Committee, "Help me Obi Wan Kenobi, you're my only hope!" should be mostly ignored, not heeded; it is not how you guide young Padawan Learners* towards becoming circuit designers.
* Jedis in training.
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Inductance alone cannot be the answer: it has to resonate with capacitors.
It cannot be output caps, since this would require a sub-nH ESL, and anyway the esr would be much too high.
I thus have to come from somewhere else
I always feel like Mark has the answer all along and is just waiting for numb nuts like me to catch up.
It did seem to me that it could not be a loop gain/phase margin issue (frequency too low and changes to compensation didn't make a difference). But it did seem to me that it was a real artefact either of the reg board or the test setup i.e. that one can't just ignore it and it is a problem that needed fixing.
My emphasis. But any damped RLC resonance dies out over time depending on the level of resistance / damping factor. So perhaps your last sentence is much more pertinent.
How do you determine that the circa 215kHz is in proportion to dI/dT when current isn't being measured? dI = 1.5. dT? I guess you look at the data sheets for the components switching the load on-off. 30ns fall time for the MCP1407, turn off delay time for the STP27N3 of 13ns followed by fall time of 2.8ns....?? I'm missing something (a lot) in the maths.
The ripple frequency has to do with the L, C and R in the circuit where you switch the current. No relation to component data sheets.
In fact if you use a battery in the same configuration you'd probably see the same ringing.
Edit: don't get hung up on the math just yet. Firs try to wrap your head around what is going on here, without worrying about the numbers themselves ;-)
Jan
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I fully expected Mark's response - both parts. Right now a mercy swoop of the light sabre would be good.
Yes, I understand the first point. What I am slow to understand is how to confirm that this particular resonance can be dismissed.
So.... we subject our regulator to a transient test, check that it doesn't break into complete oscillation, look for resonance that could be a sign of low phase margin at the UGF and also look for other resonances that could be signs of other problems (e.g. RLC resonance) within the circuit. All along we know that there will likely be some resonance due to the RLC in the combination of the circuit itself, the test jig and the wiring between, and - here's where I am slow - we can expect this resonance to be at a frequency in direct proportion to dI/dT; if this is the only resonance we witness, we can say 'all good' and move on (?)
If I get my head around the foregoing I still need to confirm that the observed resonance is in direct proportion to dI/dT.... We observe an underdamped resonance at somewhere around 230kHz; zeta = 0.06 to thereabouts. An underdamped RLC circuit will have a response of a decaying oscillation at frequency wd equal to the natural frequency wo x SQRT(1-zeta). I probably have this bit wrong but it would seem to be rather spurious accuracy in any event. So we have a natural frequency of circa 223kHz or a period of around 4.5us.
We are switching circa 1.5A (dI). I can glance at the data sheet for the MCP1407 which is driving the load pass transistor and see a 30ns rise/fall time but presumably there are other factors slowing dT for the 1.5A dI. Nonetheless I see that it's 'in the zone' of being a direct multiple of dI/dT. Is that all that's needed to dismiss this observed resonance as being expected, just related to the rise/fall time of current, and sleep more easily at night?
Right now a mercy swoop of the light sabre would be good. Yes, I understand the first point. What I am slow to understand is how to confirm that this particular resonance can be dismissed.
So.... we subject our regulator to a transient test, check that it doesn't break into complete oscillation, look for resonance that could be a sign of low phase margin at the UGF and also look for other resonances that could be signs of other problems (e.g. RLC resonance) within the circuit. All along we know that there will likely be some resonance due to the RLC in the combination of the circuit itself, the test jig and the wiring between, and - here's where I am slow - we can expect this resonance to be at a frequency in direct proportion to dI/dT; if this is the only resonance we witness, we can say 'all good' and move on (?)
If I get my head around the foregoing I still need to confirm that the observed resonance is in direct proportion to dI/dT.... We observe an underdamped resonance at somewhere around 230kHz; zeta = 0.06 to thereabouts. An underdamped RLC circuit will have a response of a decaying oscillation at frequency wd equal to the natural frequency wo x SQRT(1-zeta). I probably have this bit wrong but it would seem to be rather spurious accuracy in any event. So we have a natural frequency of circa 223kHz or a period of around 4.5us.
We are switching circa 1.5A (dI). I can glance at the data sheet for the MCP1407 which is driving the load pass transistor and see a 30ns rise/fall time but presumably there are other factors slowing dT for the 1.5A dI. Nonetheless I see that it's 'in the zone' of being a direct multiple of dI/dT. Is that all that's needed to dismiss this observed resonance as being expected, just related to the rise/fall time of current, and sleep more easily at night?
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Well there's a few ways to approach this.
You can say: what I see is the result of fast current transients in stuff around the reg; the reg shows no anomalies; done.
Or you can say: what I see is the result of fast current transient in stuff around the reg; these cloud up what I really wanted to see, namely how the reg behaves, so I will spend mucho time and money to try to clean up the stuff around the reg.
Or you can say: what I see is the result of fast current transient in stuff around the reg, but what I really want to see is how the reg behaves. So I will lower the rise/fall of those insane current transients so that I can really see what the reg does, while still exercising it harder than it ever would be exercised with those leisurely slow audio signals.
Your call, your time, your money ;-
Jan
You can say: what I see is the result of fast current transients in stuff around the reg; the reg shows no anomalies; done.
Or you can say: what I see is the result of fast current transient in stuff around the reg; these cloud up what I really wanted to see, namely how the reg behaves, so I will spend mucho time and money to try to clean up the stuff around the reg.
Or you can say: what I see is the result of fast current transient in stuff around the reg, but what I really want to see is how the reg behaves. So I will lower the rise/fall of those insane current transients so that I can really see what the reg does, while still exercising it harder than it ever would be exercised with those leisurely slow audio signals.
Your call, your time, your money ;-
Jan
I intend to have this reg power a computer motherboard. Hence the 12V, 5V and 3V3. Once I get comfortable the 12V works I can move to the other two rails (with the 12V reg supplying power to the op amps and Vrefs of the other two boards).
Now you are going to tell me I'm bonkers...
I intend to have this reg power a computer motherboard. Hence the 12V, 5V and 3V3. Once I get comfortable the 12V works I can move to the other two rails (with the 12V reg supplying power to the op amps and Vrefs of the other two boards).
Now you are going to tell me I'm bonkers...
No, I've seen people doing even stranger things ;-
But I would still say that your measurements are not very relevant to find out how the supply voltage will look like on the motherboard. There it is more a distributed load with many local bypasses....
You sure know to pick an interesting project!
Jan
This project has been/become 'more about the learning'. I had an interest to learn about electronics (zero training) but no project per se. I didn't feel I could build a power amp to better my Krell but I had been dabbling with an 'audio server' and its power supply (presently powered with a linear 12V supply with a Fidelity Audio voltage regulator to a picoPSU supply). I migrated from computeraudiophile.com (and its voodoo) to here.
I started looking at regulated voltage circuits, e.g. the Jung/Didden super regulator and wondered if I could make a very good quality high-current capable regulator in three voltages and also manage the ATX power monitoring/sequencing required (another thread here and board waiting to be powered). Luckily for me, people here and Mark in particular have provided enormous assistance.
Had I known at the beginning just what I was biting off I might have rethought my starting point. But I'm now knee deep in it all, and have learnt and am continuing to learn a tremendous amount. Hopefully I'm making some progress.
I started looking at regulated voltage circuits, e.g. the Jung/Didden super regulator and wondered if I could make a very good quality high-current capable regulator in three voltages and also manage the ATX power monitoring/sequencing required (another thread here and board waiting to be powered). Luckily for me, people here and Mark in particular have provided enormous assistance.
Had I known at the beginning just what I was biting off I might have rethought my starting point.
But I'm now knee deep in it all, and have learnt and am continuing to learn a tremendous amount. Hopefully I'm making some progress.
You working on and building "regulator".
You need to know the fundamentals behind that before take deep understanding of some parameters specified in DS.
Take an look for example this:
PID controller - Wikipedia, the free encyclopedia
Then look this animated image … ups, it's not ringing anymore
PID controller - Wikipedia, the free encyclopedia
You need to know the fundamentals behind that before take deep understanding of some parameters specified in DS.
Take an look for example this:
PID controller - Wikipedia, the free encyclopedia
Then look this animated image … ups, it's not ringing anymore
PID controller - Wikipedia, the free encyclopedia
Thanks yu3ma. Most of what we have been discussing above has to do with second order systems. Previously I found this to be a useful resource:
An Introduction To System Dynamics - Second Order Linear Systems
FWIW the above should have been wo x SQRT(1-zeta^2)
So I think I get generally damping factor, zeta, damped frequency, undamped natural frequency in second order systems natural frequency of oscillation for an RLC circuit.
If I knew the actual values for R, L and C I could calculate the natural/undamped frequency, the damped frequency and be on the look out for this. The bit I'm still missing is that in an RLC circuit - where R, L and C are unknown - we can expect and dismiss as a non-issue a resonance at a frequency "directly proportionate to the current rise/fall time dI/dT."
An Introduction To System Dynamics - Second Order Linear Systems
FWIW the above should have been wo x SQRT(1-zeta^2)
So I think I get generally damping factor, zeta, damped frequency, undamped natural frequency in second order systems natural frequency of oscillation for an RLC circuit.
If I knew the actual values for R, L and C I could calculate the natural/undamped frequency, the damped frequency and be on the look out for this. The bit I'm still missing is that in an RLC circuit - where R, L and C are unknown - we can expect and dismiss as a non-issue a resonance at a frequency "directly proportionate to the current rise/fall time dI/dT."
You working on and building "regulator".
You need to know the fundamentals behind that before take deep understanding of some parameters specified in DS.
Take an look for example this:
PID controller - Wikipedia, the free encyclopedia
Then look this animated image … ups, it's not ringing anymore
PID controller - Wikipedia, the free encyclopedia
You make the same mistake - the ringing you see is not the regulator loop....
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