ADCs and DACs for audio instrumentation applications

[JensH]

The same seems to be true for AKM, TI and Cirrus Logic.

 

[HpW]

I wonder if the "standard" DAC/ADCSs (ESS in sync mode, AKM) are sensitive to I2S jitter when the conversion is clocked by the master clock.

Well, I did not read any jitter figures on AKM for master or client mode.

Just know SDM (DSD)is very sensitive to that kind of modulation. For ESS as on DAC using Hyperstreaming may unknown too.

Even in asynch mode, 2 narrow clock frequencies may modulate/wobble in the RF regions and just look at OPPO 205 jitter..

Hp

 

[bohrok2610]

Can the slaved I2S input be mastered by bit/frameclock signals generated by the I2S output? I mean the standard duplex operation with DAC and ADC running in sync. Thanks.

Actually I think this works the other way around. The ADC (or I2S input) is the sync master and the DAC (I2S output) is synchronized with the input. This would also "solve" the isolator issue since DAC would get the MCK (and BCK & LRCK) from the ADC. The USB board would only send SD to the DAC.

 

[Evenharmonics]

Urgh. You can't resist, don't you?

He must be getting pressured from Jam.

 

[phofman]

Actually I think this works the other way around. The ADC (or I2S input) is the sync master and the DAC (I2S output) is synchronized with the input. This would also "solve" the isolator issue since DAC would get the MCK (and BCK & LRCK) from the ADC. The USB board would only send SD to the DAC.

IMO it all matters how your clocks are arranged, what generates which signal. In my project I need 768kHz samplerate at which max. propagation delays of the isolators (in my case 13ns) must be considered:

ADC
clkgen -> MCLK ADC -> ADC
clkgen -> LR_CLK -> ADC_LR_CLK slave
clkgen -> BCLK -> ADC slave
ADC_OUT -> isolator_13ns -> SAI_IN_13ns to SAI

SAI
clkgen -> LR_CLK -> isolator_13ns -> SAI_LR_CLK_13ns master to SAI
clkgen -> BCLK -> isolator_13ns -> SAI_BCLK_13ns master to SAI

DAC
clkgen -> MCLK DAC -> DAC
SAI_LR_CLK_13ns -> isolator_13ns -> DAC_LR_CLK_26ns slave
SAI_BCLK_13ns -> isolator_13ns -> DAC_BCLK_26ns slave
SAI_OUT_13ns clocked by BCLK_13ns -> isolator_13ns -> DAC_IN_26ns

 

[bohrok2610]

My original idea was to have isolation between ADC and DAC as well. So a common MCK generator could not be used without digital isolators. I do not know if this is a worthwhile goal. IIRC this was already discussed in this thread some time ago.
Actually ADC-DAC isolation was one of the reasons I put the clock behind the isolators.

 

[bohrok2610]

The I2S isolators I'm using have 250ps jitter according to the datasheet.

BTW I misread the datasheet. The above jitter was for a 25Mbps version. The 200Mbps isolators I'm using have 90ps jitter (peak eye diagram jitter) according to the datasheet.

 

[TNT]

You are fine - anyone saying something else has lost grip with reality.

//

 

[IVX]

BTW I misread the datasheet. The above jitter was for a 25Mbps version. The 200Mbps isolators I'm using have 90ps jitter (peak eye diagram jitter) according to the datasheet.

In fact, only ISO like this ADN4624(+level shifters on both sides) may completely solve the task of isolating I2S up to 768k or maybe 1500k, almost without jitter. 150M ADUM even 32/192k worked with artifacts in my setup, probably 200M will run at 192K but I have doubts if 384k as well.

 

[bohrok2610]

Sure, but very pricey (27 euros at Mouser).

 

[bohrok2610]

You are fine - anyone saying something else has lost grip with reality.

//

Yes. I fell victim to the jitterati. Makes me feel dirty.

 

[IVX]

I can't find MAX22444N(I guess you using that) in our market yet, is it cheap? Is it really work at 32/384, stable??

 

[Markw4]

I fell victim to the jitterati. Makes me feel dirty.

So its more comfortable to be the victim of prevailing dogma?

 

[bohrok2610]

I can't find MAX22444N(I guess you using that) in our market yet, is it cheap? Is it really work at 32/384, stable??

I'm now using MAX14435F. Mouser has it on stock. Seems to be stable at 384/32 and the jtest looks ok.

It's weird that almost all MCUs (or digital isolators) are out of stock everywhere. Available in mid 2022 or 2023.

 

[andrea_mori]

So its more comfortable to be the victim of prevailing dogma?

Nothing new on the horizon, perform the jtest and live happy.

 

[Evenharmonics]

So its more comfortable to be the victim of prevailing dogma?

Not dogma but level matched double blind listening comparisons and that's an awakening not victimization.

 

[IVX]

This is the 48k/24bit jtest measured at the output of my AK4490 DAC. USBI2S bridge to AK4490 so no ASRC involved.

bohrok2610, I think you need to repeat the test with near to 0dbfs level. You run at -10db and got some skirt at -140-150db, hence -130db you have something masked by noisy floor. A good result IMO <-150-155db, however, you can't say how big DAC's vs ADC jitter, so probably ADC even bigger contributor.

 

[billshurv]

So its more comfortable to be the victim of prevailing dogma?

So we are back to 'ears only' audiophiles being the new luddites?

 

[bohrok2610]

bohrok2610, I think you need to repeat the test with near to 0dbfs level. You run at -10db and got some skirt at -140-150db, hence -130db you have something masked by noisy floor. A good result IMO <-150-155db, however, you can't say how big DAC's vs ADC jitter, so probably ADC even bigger contributor.

The AK4490 dac I used in that measurement has SE output of 2Vrms so it cannot reach 0dbfs level of the soundcard I used. Besides the soundcard noise floor is quite high. Anyhow I have succumbed to the demands of the jitterati and made a new revision of the board that has the clocks outside of the isolators. I will measure that when it is ready.

 

[HpW]

I'm now using MAX14435F. Mouser has it on stock.

Yes, very very poor stock even digikey too...

Consider also the propagation delays within you time plot

Hp