AndrewT,
I am surprised that you have now discovered Nichicon UKL
These are the standard replacements that people are using to replace coupling caps(Blue Sanyo tantalums and orange ecap) in those old Pioneer/Sansui stereos.
Thx Mark for another useful transformer test jig to go with my Quasimodo
Cheers
Rick
I am surprised that you have now discovered Nichicon UKL
These are the standard replacements that people are using to replace coupling caps(Blue Sanyo tantalums and orange ecap) in those old Pioneer/Sansui stereos.
Thx Mark for another useful transformer test jig to go with my Quasimodo
Cheers
Rick
No. I guess PMs are not working for you. Maybe you have used up your entire allocation of "slots".
I have created a temporary email box that you and only you can use, for the next 48 hours. Shoot me an email there and we can communicate without PMs.
Mark Johnson
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even with DC leakage you could add a resistive divider on the input since this is called a CMOS 'Schmidt trigger'. feed back is the hysteresis. Eg don't rely on parasitic circuits . using higher voltage caps should also improve leakage
https://www.fairchildsemi.com/application-notes/AN/AN-140.pdf
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a lot depends on the traffo designer,
most traffos i have seen have primaries made that way,
but it really doesn't have to be...
in my case, since i work with tube amps,
i use a small filament transformer of about 6 volts and do my testing with that voltage....
phase checking is not rocket science,
just an application of known transformer theories.....
Not quite correct. The Schmitt trigger in Fairchild's appnote AN-140 is a 74HC14 integrated circuit, which includes hysteresis on the die. Have a look at its schematic (Figure 1 of that appnote): the transistors which provide hysteresis are P3+N3 and also P5+N5. Fairchild shows how to make an oscillator using a 74HC14 Schmitt trigger plus only one resistor and one capacitor, Fig.8.
On the other hand, the CD4069UB chip used in RingNot is an UnBuffered CMOS inverter (hence the suffix UB). It has no hysteresis, and the feedback resistor from output to input on the PCB merely accomplishes "self bias" -- setting Vin to the voltage where Vout=Vin. This biases the CMOS inverter at the highest gain point of its Vin-Vout transfer characteristic curve.
As for leakage of electrolytic capacitors, I think if you study manufacturer's datasheets you'll find they specify that leakage rises as the voltage rating increases. Generally they write the leakage spec as an equation
- Leakage_Spec_in_amps = (constant) * (Capacitance_in_farads) * (Voltage_rating)
look at fig 5a > my point is adding a divider to force bias the inverter in the middle of the logic threshold, rather than allowing stray leakage and high internal parasitics to spoil it. I reckon you didn't read that historic paper all that close.
the Schmidt trigger is classic CMOS design exercise for slower rise time signals
thx for link on leakage current, ill read it closely.
OT too bad high for voltage supplies they really are more susceptible to leakage losses of filter caps.
the Schmidt trigger is classic CMOS design exercise for slower rise time signals
thx for link on leakage current, ill read it closely.
OT too bad high for voltage supplies they really are more susceptible to leakage losses of filter caps.
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RCA invented the CD4000 series of logic gates in the 1970s.
I myself have designed quite a few CMOS logic gates (and some CMOS Schmitt triggers), so I'm quite familiar with how they're designed and how they're used. Here's one of my CMOS design patents, mentioned here simply because it has "CMOS" right in the title. Down below I've attached the syllabus of a course I taught years and years ago, about CMOS design. So although I'm grateful for your efforts to educate me about CMOS design, they are unnecessary.
I myself have designed quite a few CMOS logic gates (and some CMOS Schmitt triggers), so I'm quite familiar with how they're designed and how they're used. Here's one of my CMOS design patents, mentioned here simply because it has "CMOS" right in the title. Down below I've attached the syllabus of a course I taught years and years ago, about CMOS design. So although I'm grateful for your efforts to educate me about CMOS design, they are unnecessary.
Another YouTube video: https://www.youtube.com/watch?v=LuZh1QnegC4
This one uses a multi-channel oscilloscope.
This one uses a multi-channel oscilloscope.
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Alex, congratulations on your success! Please let me know if you ever use it on a transformer with a step-down ratio greater than 230:3 (77 to 1). That was the most severe transformer I've tried in my own testing, and that's why the design includes so much gain from node W2 to node STAGE4: about 6 to the 4th power, which is 1200X. More than enough for a 77:1 transformer. The idea is to have so much gain that the final output is driven hard into "clipping", namely, a full rail digital signal.