Input is correct - the original schematic has the orientation of the windings 'reversed' as opposed to 'mirrored'. The part in eagle goes into the schematic as it is, so it looks different.
Any thoughts or input? Not shown in the top layer which is GND. I had to pop a few 0r bridges in to separate the high current ground from the rest, so that may explain a thing or two.
Any comments? I'm super happy to keep at it for the benefit of all if there's interest? Equally, I can remove the reg - I popped it in with the idea that I could modulate the cascode ala Ven v3, but I'm not sure that's required anymore, so removing that part frees up a bit of real estate and voltage.
Any thoughts or input? Not shown in the top layer which is GND. I had to pop a few 0r bridges in to separate the high current ground from the rest, so that may explain a thing or two.
Any comments? I'm super happy to keep at it for the benefit of all if there's interest? Equally, I can remove the reg - I popped it in with the idea that I could modulate the cascode ala Ven v3, but I'm not sure that's required anymore, so removing that part frees up a bit of real estate and voltage.
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I suggested this way back in post 133. Subsequent SPICE modeling suggested it might have high DC offset at power on/off causing turn on/off thumps, so I got scared off. You can always try it and see.
...and thats not very helpful either. I suppose it's a moot point as due to operating point variability as it warms up as well.
It was also interesting to see how much PSU noise got through to the output once I built the powersupply model on... 30 - 40mV or so of ripple on the output.
So what I'm taking away from this is that cap output and a single supply are good ideas (who would have thought nelson would have know that to start with!
) for this circuit. I also read that the srpp type stages are known for not having good psrr, so the pass fet in my previous pcb design is a good idea.
It was also interesting to see how much PSU noise got through to the output once I built the powersupply model on... 30 - 40mV or so of ripple on the output.
So what I'm taking away from this is that cap output and a single supply are good ideas (who would have thought nelson would have know that to start with!
) for this circuit. I also read that the srpp type stages are known for not having good psrr, so the pass fet in my previous pcb design is a good idea.
What about pins 6 base connection ?
