So people that have a stop clock option like IanCanada pcm boards could not use this active Fdem but if took before that board ?
Correct, the bad idea of "stopped clock" means the BCK must be taken before such a board "stops the clock".
If we were doing an community "universal digital PCM system", I'd say make it an FPGA/CPLD where we massage around IIS to the various formats and additionally extract bit 16/17/18/19 (presuming we start with Bit0) to extend TDA1541 by 2 bit or 4 bit and also have an outputs for "staggered DAC's" in both amplitude and time domain.
As example, 4 pcs of TDA1541 could be used as 768kHz time domain staggered system. Add 4pcs more to allow bit's 16-31 to be converted and apply scaled down output current to the output of the upper 4pcs.
That should suit whoever snaggled all these Neve AMS SUN802 Boards with 2 X TDA1541A each off e-bay!
Or use PCM56 (still in production IIRC) staggered as upper and lower 16Bit and in time domain. With -111dB RMS noise a staggered PCM56 DAC makes sense. After making it balanced and time domain staggered we are at -119dB Noise (4 X PCM56 per channel) and thus a "32 Bit" DAC with 8pcs PCM56 per channel (53 USD per channel if buying reels) makes some sense.
Thor
Thanks,
If you ask me, after the TDA1541A my two fav dac ics are AD1862 and PCM56/58.
So in your last shematic I can't take (whatever stop clock or not) for the active FDEM to work Bck must be took before the discrete made Sim mode and not after attenuation, circuitry ?
Sorry to re ask, sometimes I have pain to follow cause my english and be understood as well. So if 15 cm for instance bck trace btween the Bck input before discrete sim mode and the FDEM flip flop input : symetrical driving with the pin8 LVDS drivers (one emitter & one receptor) is mandatory ? I will have again also a look of what you showed about this above with the CD77 close up about it.
Have you seen the question about the caps decoupling of the attenuator circuitry please : the 8 caps across +5V and Dgnd close to the attenuation resistors ?
If you ask me, after the TDA1541A my two fav dac ics are AD1862 and PCM56/58.
So in your last shematic I can't take (whatever stop clock or not) for the active FDEM to work Bck must be took before the discrete made Sim mode and not after attenuation, circuitry ?
Sorry to re ask, sometimes I have pain to follow cause my english and be understood as well. So if 15 cm for instance bck trace btween the Bck input before discrete sim mode and the FDEM flip flop input : symetrical driving with the pin8 LVDS drivers (one emitter & one receptor) is mandatory ? I will have again also a look of what you showed about this above with the CD77 close up about it.
Have you seen the question about the caps decoupling of the attenuator circuitry please : the 8 caps across +5V and Dgnd close to the attenuation resistors ?
Correct.
Run a separate line / connector to carry the BCK or MCK.
Probably overkill.
Jitter is not that relevant on the DEM, only duty cycle and stable frequency..
Not sure. We need to consider here where current flows.
1) We have a DC flowing from +5V ATT to 0V ATT, as this likely comes from the +5V of the TDA1541 the loop here is +5V to DGND and there is pure DC in this loop
2) We have current flowing from +5V ATT via the pullup resistor, series resistor and driving circuits outputs, to the driving circuits output ground and from there via the groundline back to 0 ATT. This current is signal dependent and flows when the driving circuits output is low.
3) We have current flowing from the driving circuits Vcc via the driving circuits output, series resistor and pulldown resistor to 0V ATT and from there via the groundline to the driving circuits output ground. This current is signal dependent and flows when the driving circuits output is high.
4) Whenever there is a "state change" (an edge) the capacitors charge or discharge in a loop involving the series resistor and driving circuits outputs, to the driving circuits output ground or Vcc Pin and from there via the groundline back to 0 ATT. This current is signal dependent and flows when the driving circuits output changes.
Note that (other small parasitic elements) the TDA1541 is not involved in any current loops, all these loops are between source circuit and RC.
Ideally the driving circuit's Vcc = +5V ATT (or +3.3V ATT) in which case it is clear that currents flow in and out of the driving circuits Vcc, GND and Out pin's.
Thor
Did you read seller's description of the item? Brilliant!
Btw, I accept one TDA1541 as a "thank you" from whoever grabbed all 16 pieces after I posted the links.
I wouldn't be surprised if we see them for sale on this forum.
I wish I'd been a bit quicker on the draw. I need a couple more 1541a chips.
I wish I'd been a bit quicker on the draw. I need a couple more 1541a chips.
Not pointed to you Iggy - more in general and it seems quite important - I will say that I read that differently.
If the post (after) SIM data BCK is not stopped - you can synch direct to DEM - direct from the 1541A BCK input (before or after the attenuator/??), to the flip-flop input (as you have it).
Correct, or no? _____
Reason to ask is that I want one of these PCBs, driven from the AYA 5 board ext. SIM output (usable 4ch so digital based XO all before D/A) as a second 1541A DAC to facilitate that option. I can confirm that AYA 5 SIM out (ext) does not stop BCK - further, it triggers on the correct edge - unlike Ian 15 bit (and stopped clock). There is a hack for the Ian to get back 16 bit but I never tried after more than a few say the Pedja solution was sounding better than the full ($$) Ian front end. No surprise, free capital market with motivations etc. I have the same Ians gear, will tell you later but .. hmm.
Can you double up the PCB pads for u.fl on BCK input to 1541A so one can patch short to the ext. BCK input as you have planned - or could the end user simply bridge with an unshielded wire from 1541A input BCK to the flip-flop BCK input?
I think shielded would be better, but I do not know.
.. or a two pin header (to jump in or out) direct from 1541A BCK to flipping BCK cct - but perhaps that creates an 'antennae'?.
;-)
Cheers
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Wrong , it isn't an bad idea , it's an idea you dont like , and nobody's know's why , but still an idea that work perfectly 😎
with this idea and the way John made he's glue logic , you dont need imput attenuation too , you have no trace of bck in the analog output 👍
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I measured the actual currents right at the supply/GND pins.
+5 V: 30.0 mA at -2 mA output current. 25.9 mA at -4 mA output current. 34.3 mA at zero output current.
-5 V: 39.2 mA fixed
-15 V: 26.45 mA fixed
AGND: 1.93 mA fixed
DGND: 29.55 mA fixed
I double checked the AGND current.
Gentlemen... keep it civilised.
"Stopped clock" is a great idea.
I've implemented it with no observable sonic improvements.
You'd still need slew-rate attenuation on the digital input side.
This is the consequence of the logic type used inside the chip.
DEM operation affects the sonic signature more than I'd like to admit.
As I understand it, Thorstens goal is to create a UNIVERSAL front end logic + proven facts on HW peripherals for an excellent implementation of TDA1541 based DAC.
It would certainly be possible to incorporate "stopped clock" operation into the front end core.
"Stopped clock" is a great idea.
I've implemented it with no observable sonic improvements.
You'd still need slew-rate attenuation on the digital input side.
This is the consequence of the logic type used inside the chip.
DEM operation affects the sonic signature more than I'd like to admit.
As I understand it, Thorstens goal is to create a UNIVERSAL front end logic + proven facts on HW peripherals for an excellent implementation of TDA1541 based DAC.
It would certainly be possible to incorporate "stopped clock" operation into the front end core.
Externally synchronized DEM oscillator
I tried the DEM syncing described by Bram Jacobse (origin of the circuit by Henk ter Pierick)
https://www.bramjacobse.nl/wordpress/?p=5229
The frequency divider is 1 and 1/2 74LS74A, BCK divided by 8, fDEM=176.4 kHz.
I had to change the 10k resistors to 3.3k, the original values gave garbage output signal.
There are other possibilities, I also tried the Grundig solution (also recommended by Philips). John @ecdesigns tried some direct coupling without capacitors to pin 16 and 17.
I tried the DEM syncing described by Bram Jacobse (origin of the circuit by Henk ter Pierick)
https://www.bramjacobse.nl/wordpress/?p=5229
The frequency divider is 1 and 1/2 74LS74A, BCK divided by 8, fDEM=176.4 kHz.
I had to change the 10k resistors to 3.3k, the original values gave garbage output signal.
There are other possibilities, I also tried the Grundig solution (also recommended by Philips). John @ecdesigns tried some direct coupling without capacitors to pin 16 and 17.
@J_Perkins ,
Hi, It will be at minima uf-l input as all my front-ends are uf-l to stay shielded and correct impedance. If I finish it (I very lack free time) I try to add SMA for Thorsten and further Clock à la Andréa Mori (that are possible too with uf-l).
My bad english for sure, but I asked twice and Thorsten seems to say his two flip flop circuitry for the active FDEM from Bck will work also if the material sample rate is also more than 192 K hz, i.e. up to 388 K hz thanks to the Simultaneous mode (same as Pedja Rogic) ? Hence for that, bck must be took before the sim mode in order the Fs x4 of the material works till 388 K hz original material ?
Now again you makes me doubt ?!
Aya5, does it not have a set of simultaneous 4 ufl outputs for the 2 channels multiDAC option. You just need maybe an older aya 2 from 2014 or Aya 4 w-o the USB input stage but with the uf-l I asked to Pedja Rogic to populate back in 2013/2014, which he did since AYA 2 2014 up to today ?
I do not remember if the AYA 5, 2 or 4 channels was an option ? Which one you have ? I haven't it was a little too much expensive for me.
But what I can say is I have planned embeded discrete sim à la John's from ECDESIGNS (I think his power DAC should sound even better than a TDA1541A at the end which are our ears/brain, but here we have to ask to someone who tried, I remember @maxlorenz had one)
As making a pcb is very time-consuming, as you have to translate a shematic and work on several layers and decide the trade-off, trie to see how the current loops work and where it grossly flow according the frequenciees involved. Because of that I am not sure to keep the option of stacking several FDEM board cause I really don't like the idea of two mores holes raws near he TDA14541A for the DEMs and the ones needed to decouple the stacked board efficiently to the core board (more holes and decoupling problem due to the distance the stack is creating,, not saying inductance too.
But ti could be relativly easy to give the option of two PCB with the choice of Sim and non Sim. I can imagine one with a stack of the JLSOUNDS board plus uf-l and SMA input for the I2s and the other with the discrete sim with just I2S input.
Imo some others will drop a pcb before I finsih . It can be tested, f you wish I can put you on my short beta tester list as we are on the same european area.
Edit : Thorsten clear answer to me where the Bck should be took for the FDEM flip flop of his shematic : so from the pin 2 directly seems not possible (not only a question of stop clock). Maybe I asked him with a non clear question enough ? (lost in translation effect)
[IMG alt="ThorstenL"]https://www.diyaudio.com/community/data/avatars/s/119/119890.jpg?1703518081[/IMG]
Hi, It will be at minima uf-l input as all my front-ends are uf-l to stay shielded and correct impedance. If I finish it (I very lack free time) I try to add SMA for Thorsten and further Clock à la Andréa Mori (that are possible too with uf-l).
My bad english for sure, but I asked twice and Thorsten seems to say his two flip flop circuitry for the active FDEM from Bck will work also if the material sample rate is also more than 192 K hz, i.e. up to 388 K hz thanks to the Simultaneous mode (same as Pedja Rogic) ? Hence for that, bck must be took before the sim mode in order the Fs x4 of the material works till 388 K hz original material ?
Now again you makes me doubt ?!
Aya5, does it not have a set of simultaneous 4 ufl outputs for the 2 channels multiDAC option. You just need maybe an older aya 2 from 2014 or Aya 4 w-o the USB input stage but with the uf-l I asked to Pedja Rogic to populate back in 2013/2014, which he did since AYA 2 2014 up to today ?
I do not remember if the AYA 5, 2 or 4 channels was an option ? Which one you have ? I haven't it was a little too much expensive for me.
But what I can say is I have planned embeded discrete sim à la John's from ECDESIGNS (I think his power DAC should sound even better than a TDA1541A at the end which are our ears/brain, but here we have to ask to someone who tried, I remember @maxlorenz had one)
As making a pcb is very time-consuming, as you have to translate a shematic and work on several layers and decide the trade-off, trie to see how the current loops work and where it grossly flow according the frequenciees involved. Because of that I am not sure to keep the option of stacking several FDEM board cause I really don't like the idea of two mores holes raws near he TDA14541A for the DEMs and the ones needed to decouple the stacked board efficiently to the core board (more holes and decoupling problem due to the distance the stack is creating,, not saying inductance too.
But ti could be relativly easy to give the option of two PCB with the choice of Sim and non Sim. I can imagine one with a stack of the JLSOUNDS board plus uf-l and SMA input for the I2s and the other with the discrete sim with just I2S input.
Imo some others will drop a pcb before I finsih . It can be tested, f you wish I can put you on my short beta tester list as we are on the same european area.
Edit : Thorsten clear answer to me where the Bck should be took for the FDEM flip flop of his shematic : so from the pin 2 directly seems not possible (not only a question of stop clock). Maybe I asked him with a non clear question enough ? (lost in translation effect)
[IMG alt="ThorstenL"]https://www.diyaudio.com/community/data/avatars/s/119/119890.jpg?1703518081[/IMG]
Previously: Kuei Yang Wang
Joined 2002Correct.
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@Alexiss ,
It's above my head, but is the attenuator circuitry making not this slew rate things low enough already ? I remember Thorsten few post ago saying stop clock could be a so-so idea ?!
I do wonder about slewing and glitches more about the current output of the DAC to be tamed before the first input pin of teh I/V circuitry. But Thorsten Loesch circuitry in his explanation seems to focus on that too!
It's above my head, but is the attenuator circuitry making not this slew rate things low enough already ? I remember Thorsten few post ago saying stop clock could be a so-so idea ?!
I do wonder about slewing and glitches more about the current output of the DAC to be tamed before the first input pin of teh I/V circuitry. But Thorsten Loesch circuitry in his explanation seems to focus on that too!
Today I spent some time for measuring THD vs temperature. I used a freeze spray, a hairdryer and an IR handheld "gun" thermometer. I measured THD at full scale and at -60 dB. The free air temperature of the TDA was 49 °C. I freezed it to +15 °C and heated up to +60 °C. The ambient was 24.5 °C.
The result is surprising even for me:
There was no change of THD at cooled down, neither at heated up, compared to the initial state.
Nevertheless, I will use a copper heatsink, because it is cool (pun intended), and it provides shielding against EMI. The heatsink should be connected to GND.
Quite informative Icsaszar,
My theory (so not tested and reitered) is the heatsink does nothing from an air EMC point of view (emitter or victim) because it is too much open, but when tied to a gnd pin of the TDA (pin 5 or 14) changes the impedance of the TDA ground internal as external (the pcb) close and that SEEMS clearly hearable.
If shielding, it should be closed around the TDA tied and proof to the top layer. So there is a non negligle chance that has nothing to see with EMC and now with what you say with temp ! I think maybe it's a level impedance ground thing or at best a current thing.
my two cents.
Edit : the looking is personal, myself I find cooler (pun intended too) to see the top and pedigree of the TDA chip, I even want to put heatsink marmelade on a crowned TDA1541A or a 1987/88 from Taiwann !
If people wants to thanks me with what is now called "Alexandre paradox", I accept a two crowns which I haven't yet 🙂 😎😍
My theory (so not tested and reitered) is the heatsink does nothing from an air EMC point of view (emitter or victim) because it is too much open, but when tied to a gnd pin of the TDA (pin 5 or 14) changes the impedance of the TDA ground internal as external (the pcb) close and that SEEMS clearly hearable.
If shielding, it should be closed around the TDA tied and proof to the top layer. So there is a non negligle chance that has nothing to see with EMC and now with what you say with temp ! I think maybe it's a level impedance ground thing or at best a current thing.
my two cents.
Edit : the looking is personal, myself I find cooler (pun intended too) to see the top and pedigree of the TDA chip, I even want to put heatsink marmelade on a crowned TDA1541A or a 1987/88 from Taiwann !
If people wants to thanks me with what is now called "Alexandre paradox", I accept a two crowns which I haven't yet 🙂 😎😍
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I meant I even DON't want to put heatsink white thermal marmelade on the top of a TDA (that's why I asked if fan coulld be usefull or not, btw)
Hi,
Why ? You want balanced or needs higher current output ?
I remember John measured than the too much intrinsec jitter and noise inside the TDA1541A were not favoured a symetric or multiple TDA1541A on board. (And most of what he has were old Taiwan made)
I can add it is also from a pcb layout development an even worse idea....
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