It is also, in it’s simplicity, quite easy to build point to point or on a perf-board, and to experiment with. Very cool, and great sounding. The Iron Pre takes it a big step further, but if you want it to look messy, steer clear of MZM’s boards 
We all want an Iron Pre, but the R2 is also really cool in itself. Just be sure to keep psu wires short, and if in doubt include some caps really close to the buffer. Makes a big difference. No limits to perfecting it, as with everything.
We all want an Iron Pre, but the R2 is also really cool in itself. Just be sure to keep psu wires short, and if in doubt include some caps really close to the buffer. Makes a big difference. No limits to perfecting it, as with everything.
Thank you all for many comments. Just to make clear, I meant DCB1 as "symmetrical PSU B1". It looks people live in separate threads for DCB1 and for B1R2. I'm not much tempted to build original B1 as I don't have good caps in my drawer. I wish building a buffer from my junk box. Iron Pre appears so nice, but too gorgeous to me. I need only a small simple buffer with volume control, not a pre-amplifer. Integrated powersupply in the same board is also too much as I will probably use regulators from my stock, 3045 or 1761 or whatever low noise type. As Andy suggests, I think perf-board will be enough for this scale of circuit. I would make sure locating ps caps very close to buffer. Thanks for that tips.
I built my B1 R0 using TDK film caps I found in someone else's drawer, left over from some sort of solar cell rectifier project. One doesn't have to buy boutique to make this topology sound just fine.
Indeed. The original B1 used the very reasonably priced Axon caps.
Hello,
I found something strange in simulating B1 Rev.2 parameters in LTSpice. I found the distortion becomes lower when the input resister is lower and also when the 50ohm trimpot is increased on positive side. I would like to know if this is due to some issues of simulation and not real performance improvement, or it may be true. The problem may be on my use of LTSpice (note that I'm a beginner) or the models used in the simulation or any limitation of LTSpice. At least I tried several different models of K170/J74, and obtained the same tendency.
This is the original circuit and commands. The balance of 50 ohm trimpot was adjusted in 0.1 ohm level to minimize the DC component on the output to 0.2mV.
Then I got 0.000114% of total distortion
When I reduced the input register R4 to 33 Ohm, the distortion became 0.000023% ! It became 1/5. Does it make sense? Can we implement it to my buffer? I think there was reasons to have 1k of input register, and reducing that so significant might cause some issues. Theoretically lowering input register is effective to suppress the noise level, so maybe preferred.
After that, I made typo in adjusting 50 ohm trimpot, and made that to 250 ohm total and severely unbalanced. Then surprisingly I saw significant improvement of distortion.
Look here, the total distortion became 0.000009% !! As there is large DC offset of 0.14 V, we can't use this circuit as it is. Adding a cap like original B1 may solve DC offset issue. However is this improvement is understandable as the behavior of this circuit? Can this be real improvement?
I can imagine somebody may say "why don't you try". Yes, I can make trial of this kind of tweaks on the real circuit (the second option must be decoupled with a cap of course). However I don't have any gear to measure such low distortion. I don't have golden years to recognize the difference between 0.0001% and 0.000009%. So unless this causes major degradation from original B1 Rev2, I'm afraid that I can't evaluate the difference between them. So I would ask any of your experts if this is theoretically true but there are reasons not to do so, or this was caused by my wrong operation or any other reasons simulation specific, thus shouldn't be considered....
I found something strange in simulating B1 Rev.2 parameters in LTSpice. I found the distortion becomes lower when the input resister is lower and also when the 50ohm trimpot is increased on positive side. I would like to know if this is due to some issues of simulation and not real performance improvement, or it may be true. The problem may be on my use of LTSpice (note that I'm a beginner) or the models used in the simulation or any limitation of LTSpice. At least I tried several different models of K170/J74, and obtained the same tendency.
This is the original circuit and commands. The balance of 50 ohm trimpot was adjusted in 0.1 ohm level to minimize the DC component on the output to 0.2mV.
Then I got 0.000114% of total distortion
When I reduced the input register R4 to 33 Ohm, the distortion became 0.000023% ! It became 1/5. Does it make sense? Can we implement it to my buffer? I think there was reasons to have 1k of input register, and reducing that so significant might cause some issues. Theoretically lowering input register is effective to suppress the noise level, so maybe preferred.
After that, I made typo in adjusting 50 ohm trimpot, and made that to 250 ohm total and severely unbalanced. Then surprisingly I saw significant improvement of distortion.
Look here, the total distortion became 0.000009% !! As there is large DC offset of 0.14 V, we can't use this circuit as it is. Adding a cap like original B1 may solve DC offset issue. However is this improvement is understandable as the behavior of this circuit? Can this be real improvement?
I can imagine somebody may say "why don't you try". Yes, I can make trial of this kind of tweaks on the real circuit (the second option must be decoupled with a cap of course). However I don't have any gear to measure such low distortion. I don't have golden years to recognize the difference between 0.0001% and 0.000009%. So unless this causes major degradation from original B1 Rev2, I'm afraid that I can't evaluate the difference between them. So I would ask any of your experts if this is theoretically true but there are reasons not to do so, or this was caused by my wrong operation or any other reasons simulation specific, thus shouldn't be considered....
You have a mistake in your schematic. Check your p-channel jfet.
Ah thank you, yes it was wrong, however JFET's are usually symmetric (or almost symmetric?) and exchanging them doesn't make difference in this behavior. Still low input gate register leads lower distortion, and applying some DC offset made further reduction of distortion. By optimizing trimpot, I got 0.000004% with 75 mV off-set.
Perhaps. But in what sense is that relevant, when needing an output cap to be used?
The input resistor is there to reduce chances of oscillation. If you prefer oscillation over distortion, go ahead. I found it should not be reduced much below 300R.
The input resistor is there to reduce chances of oscillation. If you prefer oscillation over distortion, go ahead. I found it should not be reduced much below 300R.
Hi Andy, I've often wondered about adding extra resistance to the j74 jfet (source?) to "match" transconductances of them both but it doesn't seem to be of any significance, no?
Hi Andy, I agree, my aim to go B1 Rev.2 was to eliminate large cap as it's usually costly and space eater (I want to make this very compact). Adding large cap in LTSpice doesn't degrade the distortion, but in real life it should have certain negative impact.
And thank you for the reason of the input resister min size. Probably that oscillation can't be checked with LTSpice, or it requires a lot of influencing factors like L or C of wires between components? To be safe, I'd start around 300R when I will make it.
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BTW probably I'm not evaluating this circuit properly. In this simulation, no buffer = just a wire achieves the best result, since this is a buffer without gain. The reason of powered buffer is to make the output signal quality independent to the input volume's position, or to make it robust to the long wire's influence? Or should I consider capacitance and impedance of the load to measure buffer's benefit?
Using a VC, an active buffer will be way better than wires+VC. No need to measure it, a buffer will make life much easier. You are correct regarding difficulty simulating oscillation, it will as you say be dependant on what is upstream.
If wanting to get rid of components and increase damping factor, and lower distortion even more whilst increasing xcon, double up on the jfets (very well matched) and remove the series output resistor. You can also remove the jfet source resistors as long as they are very well matched. I did and achieved 1,5mV dc offset without pot/source degen. Smooth.
If wanting to get rid of components and increase damping factor, and lower distortion even more whilst increasing xcon, double up on the jfets (very well matched) and remove the series output resistor. You can also remove the jfet source resistors as long as they are very well matched. I did and achieved 1,5mV dc offset without pot/source degen. Smooth.
Distortion will be lower, but the less degen the more natural sound, some say.
In this design the 50R pot does this job, providing unequal resistances to each source pin so as to null DC offset.
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Plus, according to pa’s writings, jfets also provide a linear output sans degen. So win-win, if you have very well matched fets.
Excuse me, as I told I'm new to LTSpice, I had made a clear mistake. Some of you might realized it. I put "1m" as the R5 instead of "1Meg".
However it was not fundamental reason why I found improvement of distortion by imbalanced zero offset. Even after I corrected R5 to 1Meg, the same tendency was confirmed. Still smaller R4 and larger R1 lowered the distortion.
When I reproduce the input volume, 20k volume at middle position, that strange phenomena of improvement by imbalanced zero trimmer disappeared. Reduction of R4 to 33 ohm changed distortion to 0.000349% only for 9/10. There is no benefit to go below 300 Ohm taking risk of oscillation. Adjusting R1 improves the distortion figure only in non-measurable level.
By the way I found quite same circuit idea in Japanese monthly magazine of electronics "Transistor Gijyutsu (Technology)" 2000 April, as a name of "Zero bias complementary Source follower". Separating gate resister make any improvement? No off-set adjustment in relying on JFET matching.
Another one from 1999? Is "Audio Electronics" a magazine? Looks it's from June/1999 edition. Right side schematic shows no resistor around JFET. The left side circuit appear similar to DCB1, but with some extra large resistor and cap between two JFETs. It's written as improvement from exact DCB1 type shown above in this document.
http://raylectronics.nl/pdfs/Audio_Electronics_JFETs.pdf
Another one from 1999? Is "Audio Electronics" a magazine? Looks it's from June/1999 edition. Right side schematic shows no resistor around JFET. The left side circuit appear similar to DCB1, but with some extra large resistor and cap between two JFETs. It's written as improvement from exact DCB1 type shown above in this document.
http://raylectronics.nl/pdfs/Audio_Electronics_JFETs.pdf
Your second image is part of Erno Borbely's article "JFets: The New Frontier".
Worth reading it over and over again.
Worth reading it over and over again.