There is a great difference between our FIFO Lite and Ian's FIFO: the FIFO buffer is slaved to the master clock that resides in a different time and electrical domain.
In our FIFO the LRCK comes directly from the master clock, it does not cross the FPGA, so it's well isolated from the source.
Just curious, wouldn't gray code do the trick, or at least improve on pure R2R?
We have no transiction on the first MSBs since we use sign magnitude notation, so the glitch should be already less than in a classical 2's complement notation DAC.
OT but in your (lovely) streamer project would you mind sharing the source of those round hdmi and ethernet sockets please. Beats cutting square holes!
Hi,
Could you include a mode which outputs an SPI format for the new TI R2R DAC11001 ? Im working on a MCU based solution at the moment, but of course it would be much better to have this capability in the FIFO, so no further conversion would be needed.
Could you include a mode which outputs an SPI format for the new TI R2R DAC11001 ? Im working on a MCU based solution at the moment, but of course it would be much better to have this capability in the FIFO, so no further conversion would be needed.
Thankyou
Andrea I just noticed my information isn't in the spreadsheet however I did receive and invoice and is paid. I shall update spreadsheet
Andrea I just noticed my information isn't in the spreadsheet however I did receive and invoice and is paid. I shall update spreadsheet
RMAF11: Digital Jitter and Volume Controls, Martin Mallison, CTO, ESS Technology - YouTube
Found this old video. Watch from 15:55 onward on jitter. It does explain in the video that PLL does not isolate the source clock, and PLL has weaknesses.
It'll be very interesting to see the performance of your FIFO front end, vs. Soekris' front end.
Found this old video. Watch from 15:55 onward on jitter. It does explain in the video that PLL does not isolate the source clock, and PLL has weaknesses.
It'll be very interesting to see the performance of your FIFO front end, vs. Soekris' front end.
Last edited:
I believe it was enough obvious, a true buffer is needed to isolate the DAC from the source.
I'm curious too.
Preliminary measurements
I attach some phase noise plots of the FIFO Lite:
- MCLK output
- BCK output (FIFO Lite + Reclocker)
- LRCK output
- Comparison (including the base DRIXO 24.576 MHz oscillator)
I attach some phase noise plots of the FIFO Lite:
- MCLK output
- BCK output (FIFO Lite + Reclocker)
- LRCK output
- Comparison (including the base DRIXO 24.576 MHz oscillator)
Attachments
