So, if I understood this correctly, in case of my CD-player (4x OS->176Khz data frame), sound-quality might be improved because of the 1:4 frequency ratio between WS and fDEM enabling the DEM to work better.
The 100pf would give a 1:5 (WS:fDEM) ratio and therefore be a better value than the factory installed 680pf.
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These can be found in the data sheets of SAA7020, SAA7220B. The bit clock is stopped after 16 periods. I replaced the TDA1540P for a TDA1541A in my player after bypassing the SAA7000 (my first attampt of NOS), and it worked fine. So the data formats are compatible.Can anybody draw the logic formats, without timing, for COB format for TDA1541A and input format of TDA1540? Is the difference only in word bit lenght?
or maybe something else?
From the SAA datas the bit clocks are stopped?
Absolutely, thanks for that idea. I am listening to that configuration a week already, I have only added two 6K8 resistors /thanks to John/. I decided to go further logically - NO OPAMPS .The only problem is the low current out therefore I decided to go for "pyggyback"ing two chips /thanks to Ove/ in order to push the current output and go straight to the grid of a tube - the passive I/V resistor directly on the grid's pin on the bottom.
Please comment ?
Cheers,
Ignat
Sorry I havn't mentioned it - now i have 68R and after the pyggybacking I plan to go for 33R - you are right, thanks
The 100pf seems a bit too scary for me right now, but if there are good enough reasons for trying... why not
Please advise us about your listening tests /no scope please/after you went to different values of that cap - 470 and 100 pf.
Regards,
Hi oshifis, I took a quick look into saa7220 datas
and it seem that works in I2S input to I2S output data format.
Or output format same as input format?
If You exchange the TDA1541A to TDA1540, that could indicate that TDA1540 can work with I2S format?
I which mode TDA1541A was in Your example - I2S or Sim. COB?
and it seem that works in I2S input to I2S output data format.
Or output format same as input format?
If You exchange the TDA1541A to TDA1540, that could indicate that TDA1540 can work with I2S format?
I which mode TDA1541A was in Your example - I2S or Sim. COB?
Hi Zoran,
SAA7220B supports I2S only. TDA1540 supports offset binary format only. TDA1541A supports both format. I converted an old (TDA1540) player to NOS by removing the SAA7030 digital filter (that supports 14-bit only), selected 16-bit mode on SAA7000 (this chip supports offset binary only), and selected offset binary format on TDA1541A.
SAA7220B supports I2S only. TDA1540 supports offset binary format only. TDA1541A supports both format. I converted an old (TDA1540) player to NOS by removing the SAA7030 digital filter (that supports 14-bit only), selected 16-bit mode on SAA7000 (this chip supports offset binary only), and selected offset binary format on TDA1541A.
So TDA1540 have
COB format
14bit word length,
stopped sys-clk (bck).
similar DEM circuit like 1541A...
.
Until now I done some work in PSpice.
I have some TDA1540 chips, and I will try to make them work with glue logic. Somehow.
I inverted MSB from I2S bus with serial to parallel logic.
Made stopped bck 14 pulses, and (16x for 1541A in COB format)
.
But it is unclear about LE.
In 7000 and 7030 outputs, acc to datas, it is app 3.5 pulses BCK before MSB?
Or it could be in time place like MSB?.
.
Anyway I will first try to built and measure digital signals.
I used references from Philips I2S doc.
made first WSD, WSP lines, add Edge detect line.
And AD app note 207.
.
(I am thinking to try PMD100 before TDA1540
*based on Guido T example with PMD100-TDA1541A)
.
Thanks, I was not sure about format of TDA1540.
COB format
14bit word length,
stopped sys-clk (bck).
similar DEM circuit like 1541A...
.
Until now I done some work in PSpice.
I have some TDA1540 chips, and I will try to make them work with glue logic. Somehow.
I inverted MSB from I2S bus with serial to parallel logic.
Made stopped bck 14 pulses, and (16x for 1541A in COB format)
.
But it is unclear about LE.
In 7000 and 7030 outputs, acc to datas, it is app 3.5 pulses BCK before MSB?
Or it could be in time place like MSB?.
.
Anyway I will first try to built and measure digital signals.
I used references from Philips I2S doc.
made first WSD, WSP lines, add Edge detect line.
And AD app note 207.
.
(I am thinking to try PMD100 before TDA1540
*based on Guido T example with PMD100-TDA1541A)
.
Thanks, I was not sure about format of TDA1540.
The rising edge of LE will converts the data to analog. LE should go HIGH after the last BCK pulse has gone LOW.
re #5127
Some people might be a bit confused by Niamex's use of the 68R I/V resistor connected directly to the output pins of the 1541A dac chip, and it brought to mind Thorsten use of a 100R resistor in one of his early designs when the theoretical value appears to be 12R for the +/-25mV compliance?
Why is the theoretical limit exceeded by so much? and what happens to the sound when the +/- 25mV o/p pin specification is ignored?
Well, it's actually a lot simpler than you would imagine - most recordings don't actually come close to the maximum +/-2mA level that would produce this theoretical 25mV compliant limit, except for some transients (and some of those ghastly 'line compressed' mixes) so the playback doesn't often actually reach this +/- 2mA on the o/p pins on most audio playback - and yes, this will vary with different music ...
On the other hand, if you do use a 12 -15R I/V resistor that will only generate that max +/- 25mV, it isn't particularly difficult to build a gain stage that has a 20+dB gain to bring this 25mV up to about 2V rms (phono/mic preamps do much higher gain than this with ease) - the main problem here is the higher gain stage is quite a bit more complicated/difficult/expensive and so a higher I/V resistor value is a quite reasonable compromise - a 36R value is quite common, particularly a 'better quality' component.
Perhaps some of our more technical people can add more details about this ...
Some people might be a bit confused by Niamex's use of the 68R I/V resistor connected directly to the output pins of the 1541A dac chip, and it brought to mind Thorsten use of a 100R resistor in one of his early designs when the theoretical value appears to be 12R for the +/-25mV compliance?
Why is the theoretical limit exceeded by so much? and what happens to the sound when the +/- 25mV o/p pin specification is ignored?
Well, it's actually a lot simpler than you would imagine - most recordings don't actually come close to the maximum +/-2mA level that would produce this theoretical 25mV compliant limit, except for some transients (and some of those ghastly 'line compressed' mixes) so the playback doesn't often actually reach this +/- 2mA on the o/p pins on most audio playback - and yes, this will vary with different music ...
On the other hand, if you do use a 12 -15R I/V resistor that will only generate that max +/- 25mV, it isn't particularly difficult to build a gain stage that has a 20+dB gain to bring this 25mV up to about 2V rms (phono/mic preamps do much higher gain than this with ease) - the main problem here is the higher gain stage is quite a bit more complicated/difficult/expensive and so a higher I/V resistor value is a quite reasonable compromise - a 36R value is quite common, particularly a 'better quality' component.
Perhaps some of our more technical people can add more details about this ...
I think the output compliance voltage of 25mV is specified to guarantee their "dynamic" accuracy(glitch size, settling time and THD)
because TDA1540/1's glitch occasion is inherently affected by output pin voltage.
http://www.diyaudio.com/forums/digi...e-nos-dac-using-tda1541a-492.html#post3616945
(in comparison, R2R DAC is affected static accuracy by output pin voltage variation)
Therefore, in passive IV circuit, the glitch size is affected sample values before and after MSB transitioning.
However I do not have any experience that glitch variance in passive IV circuit affects spec or SQ.
because TDA1540/1's glitch occasion is inherently affected by output pin voltage.
http://www.diyaudio.com/forums/digi...e-nos-dac-using-tda1541a-492.html#post3616945
(in comparison, R2R DAC is affected static accuracy by output pin voltage variation)
Therefore, in passive IV circuit, the glitch size is affected sample values before and after MSB transitioning.
However I do not have any experience that glitch variance in passive IV circuit affects spec or SQ.