Variation on the JC-2 preamplifier

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#101
I found the dioda-resistor connection like in Cello use in this schematic : D38-39-40-41

What is the function of this Dioda-resistor?
 

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#103
scott wurcer said:


That's along the same lines. I was thinking of a resistor crossing the "H" too. There are some magic values that give a flat transfer function that we use in some op-amp inputs. Along the same lines as the magic output ballast resistors. I once had a copy Pedersons original hand written derivation. FET's don't have the same cancellation, but you can create a pretty wide linear region.
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Cool. Are there any datasheets for these opamps containing simplified schematics?
I'm curious to learn how the dual bipolar differentials are biased, as well as the VAS stages if each LTP is loaded with a current mirror.
 
#105
Tom, Dick and Harry fun aside,

any idea how effective the series diode thing between the driver emitters in Lumanauw's schematic is ?

David,
the picture reads Technics, that's not the SE-A1, is it ?
(i've seen that crossfeed correction circuit in a 3d schematic)

Jan, who misses J. Kool with you around.
 

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#106
Sorry if my joke is not understood.
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Naah!! Mr. AD797, no reason to worry at all. I feel deeply honoured that you bothered to reply to me!

It's just that I have an inexplicable preference for discrete designs - for whatever reason - so that I really have no clue about opamps or chipamps. I read this phrase now and then, but never cared to ask, but you made me curious 😀

Thank you and all the best, Hannes
 
#109
syn08 said:

---snipped---

And that's about it. If you are looking around Idss (that is, around Vgs=0) then gm0=2*Idss/Vt. At Vgs between Vt and 0 (and no, forward biasing the JFET is not a good idea, you are pushing your luck for some extra gm, that after all depends only linearly on Vgs) the transconductance is larger for devices with lower Vt.

---snipped---
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Dear syn08,

I came late on this thread so sorry for an untimely response to your post.

I think some people on this forum may be interested for a consequence of driving a N-ch JFET to positive bias. Here is a figure copied from Mr Toru Kuroda's book, "Introduction to Transistor Amplifier Design" 1986, ISBN 4-8443-0168, pp 187. (Unfortunately, the book is written in Japanese.) The graph displays the actual measurement of the Id for 2SK170BL.

Apparently, you can foward bias this JFET without much trouble. The problem is gate leak current (roughly 1 nA at Vgs = 0.35V at 25$B!k(BC, increases with temperature). The author recommends to use positive bias at less than 0.2V to keep gate leak current in pA range. The book also has a graph showing the actual measurement of the gate leak current. The graph proves Mr Curl's claim on JFET use is valid one, I think.

Best regards,
Satoru
 

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#110
Thanks Satoru. You have been very helpful to me. I used a curve tracer to verify my results, but a real graph is much better. It is interesting that even American long gate fets can be forward biased and they will work pretty well, from a very low impedance drive. They just keep working just like transmitter tubes do.
 
#111
satoru said:
I think some people on this forum may be interested for a consequence of driving a N-ch JFET to positive bias. Here is a figure copied from Mr Toru Kuroda's book, "Introduction to Transistor Amplifier Design" 1986, ISBN 4-8443-0168, pp 187. (Unfortunately, the book is written in Japanese.) The graph displays the actual measurement of the Id for 2SK170BL.

Apparently, you can foward bias this JFET without much trouble.
Click to expand...
Please clarify what I think I'm seeing in the graph.
The Idss (~=7mA) is shown when the Vgs=0 and the gate voltage can be taken up or down from the Vgs=0 bias point.
The conventional bias is negative thus turning off the FET as the gate voltage goes down.
The graph shows that when the gate is taken high it turns the FET on , to draw substantially more current.

??
 
#113
Dear John,

It is nice to hear that the graph was a help. In my personal opinion, your circuits are simple and elegant!
By the way, the book I quoted from is very well written and I see explanations for some ideas taken from your circuit.

Dear Andrew,

When an AC signal comes in, the output current of JFET goes up and down, which is fed into next stage. The input range is restricted by the difference of DC bias point to Vgs(off). By setting DC bias point closer to Vgs=0, the input range can be larger, in addition to lower noise and higher gm (same thing, actually) but with higher gate excess current which may have to taken care of.

Dear all,

Electronics is not my profession. I'd love to be corrected for my mistakes so please let me know where there are! Thanks.

AndrewT said:
Please clarify what I think I'm seeing in the graph.
The Idss (~=7mA) is shown when the Vgs=0 and the gate voltage can be taken up or down from the Vgs=0 bias point.
The conventional bias is negative thus turning off the FET as the gate voltage goes down.
The graph shows that when the gate is taken high it turns the FET on , to draw substantially more current.

??
Click to expand...

Regards,
Satoru
 
#114
satoru said:

The problem is gate leak current (roughly 1 nA at Vgs = 0.35V at 25$B!k(BC, increases with temperature).
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This is precisely why positive biasing the JFET gate is a bad idea. It's not necessary the gate current, but the gate current temperature dependency. The last thing you need in your amp is to care about thermal effects in the input stage.

Look at this reference:

High-temperature operation of junction field-effect transistors in the forward-bias mode
Ettinger, G.M.; Joslin, P.
Electronics Letters
Volume 2, Issue 7, July 1966 Page(s):266 - 267
 
#118
Yeah, I recognized that we are talking two different things, too: biasing near the Vgss = zero (or near) while biasing at positive (foward) Vgss. Since the temperature issue surfaced, I'll post a graph (from the same book, same page). The solid line is at room temperature (25$B!k(BC) and the broken line is an estimate at 100$B!k(BC. Based on this estimate, the author of the book recommends occasional swing to positive side to be less than 0.2V. He also mentions that some commercial amplifiers are biased at Vgss=zero.

Regards,
Satoru
 

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#119
h_a said:
Well what do you actually think of Tom Colangelo as designer?

Interestingly, while he is mentioned now and then, nobody says a word or two about his engineering abilities/designs; also the thread about his Cello Encore (including the schematic) was quite silent. I am not sure why this is so, the design itself is unusual and interesting.

Why so?

All the best, Hannes


Cello Encore schematics (2 pages)

discussion on DIYAudio (starts after a couple of postings)
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Would anyone tell where is the feedback network of the these Encore schematics? According to these schematics the -In is opened and has no connection to the feedback network.
 
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