If I put my notes here, I might be able to find them again later!
B-board v2 line driver : development circuit
Original version is here.
I've been meaning to get around to updating this by folding in the improvements to the diamond buffer stage made during development of the Sapphire 3 headphone amplifier. Here is the first look of the bboard v2 under LTSpice.
I've gone back to simple emitter resistors on the input, running under much lower current to keep the input impedance high. The output is simplified to a basic Sziklai compound transistor pair with the bulk of the bias current running in the second transistor.
In terms of distortion, for line level output level, CCS loaded input has no advantage. I'll have to double-check PSRR and a few other things before signing off on this version though.
FYI only, not a production circuit.
I've been meaning to get around to updating this by folding in the improvements to the diamond buffer stage made during development of the Sapphire 3 headphone amplifier. Here is the first look of the bboard v2 under LTSpice.
I've gone back to simple emitter resistors on the input, running under much lower current to keep the input impedance high. The output is simplified to a basic Sziklai compound transistor pair with the bulk of the bias current running in the second transistor.
In terms of distortion, for line level output level, CCS loaded input has no advantage. I'll have to double-check PSRR and a few other things before signing off on this version though.
FYI only, not a production circuit.
Total Comments 7
Comments
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I just checked PSRR - current sources improve the LF PSRR over 20dB (from ~50dB to ~76dB) but it starts degrading around 1kHz due to the 100pF caps.Posted 1st November 2015 at 03:26 AM by abraxalito
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Do you mean C1, C2 in the circuit? I'm surprised they'd have any influence on anything below 100 kHz.
~25 dB extra PSRR from the current sources is about what I was expecting ... though I was hoping it was less so I could convince myself that the simpler resistive loading would be OK.Posted 2nd November 2015 at 01:04 PM by rjm
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Yep, I meant C1,2. They dominate the PSRR above 1kHz when CCSs are used. With resistors the effect of these caps isn't seen.Posted 4th November 2015 at 01:15 PM by abraxalito
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I've had a chance to confirm that now. About 50 dB for resistors and 75 dB for a CCS, but the PSRR of the CCS version starts to drop above 5 kHz due to C1 C2, while it drops above 30 kHz when C1 C2 are removed. At 100 kHz the PSRR is 50 dB and 66 dB respectively.
Thing is, the response peaks badly when those capacitors are removed.
What to do, what to do?Posted 5th November 2015 at 01:32 AM by rjm
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Here's a crazy notion - replace R11 and R12 with 1.4mA CCSs. Then you can have your 100pF caps to iron out the 10MHz+ peaking and still get decent PSRR - 76dB at LF and still 64dB @ 20kHz. But two more CCss means more complexity.... But transistors are really cheap when SOT23s so the cost-up is pretty insignificant.
An alternative comes to mind - split R11/12 into two and decouple the centre point with a big enough cap. Not tried that but should also improve HF PSRR.Posted 6th November 2015 at 02:17 AM by abraxalito
Updated 6th November 2015 at 02:23 AM by abraxalito -
Increasing the impedance of R11,12 by using CCS does work as you say ... the trick is the voltage drop across those resistors is only one diode drop, and it's a bit tricky to make a CSS unless you have at least two drops worth of voltage to play with.
Will look into the alternatives suggested.Posted 10th November 2015 at 12:38 AM by rjm
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Ah - that's a good point, I only simmed with the 'virtual' current sources in LTspice, not real ones. I suppose you could turn the output transistors into Darlingtons to gain a bit more leeway for a real CCS.Posted 10th November 2015 at 01:47 PM by abraxalito
