Edmond Stuart said:
Hi Edmond,
You didn't overlook anything, I just didn't post the graph that showed the problem
. It was in the curves of Id vs. Vds with Vgs as parameter. The drain current was changing too much with Vds, even though I had the LAMBDA parameter set to zero. This was caused by using the default values of WETA and LETA. I changed them both to zero, to eliminate the modeling of "charge sharing", then used only LAMBDA to control the simulated output conductance.Now the output conductance looks good, but in the triode region, the ON resistance is way too low (factor of 10 or so). I don't know how to fix this. I had this same problem with the simple level 1 model. At that time, I was wondering if I should put a small resistor in the drain to make the ON resistance correct. I am wondering about that again now. Otherwise, the Id-Vgs curve looks good, and the variation of Id with Vds looks good outside of the triode region.
I've also been looking at the capacitances. I made L=2e-6 and W=5e-4. I set COX to 1e-6, which is the smallest recommended value in the EKV manual. To get the required transconductance, I just increased KP, which does not affect capacitance. This combination makes the internal capacitances extremely small, on the order of tenths of a pF or maybe less. So the external capacitors in the subcircuit will dominate.
I am flying to Arizona to attend my niece's wedding, so I won't be back until next week. I've attached the Excel file that has the EKV code, along with captured data from the datasheet, and simulated data in case anybody wants to look at it. The code is pretty messy, as it was copied from the VHDL-AMS code on the EKV web site.
andy_c said:
Andy,
I might miss here something, but unless expressed in some imperial units, Cox=1e-6 doesn't make much sense.
Cox is defined as Eox/Xox where Eox is the silicon dioxide absolute permittivity (8.856e-12*3.9 Farad/Meter) and Xox is the gate oxide thickness, in meters.
A quick calculation reveals that for Cox=1e-6 Farad/meter^2, Xox is 3.45e-5 meters or 34.5 micrometer which is absolutely huge.
If Cox=1e-6 is expressed in the CGS units of F/centimeter^2, then Xox is 3.45 nanometer or 34.5 angstrom, which way out of the range (too small) for a MOSFET power device.
A realistic value for the gate oxide thickness is 700 angstrom or 0.07 micrometer, leading to a value of Cox of 5e-4 Farad/meter^2 or 5e-8 Farad/centimeter^2
I realize this is a non-physical situation.
The idea was to make the computed capacitances for the intrinsic device as low as possible. Then the vertical MOSFET will be modeled as a subcircuit with an external nonlinear gate-drain capacitance given by the same formula LTSpice uses for the Cgd in their proprietary VDMOS model. This would use a "Q=" formula for the nonlinear Q(v) of a discrete capacitor. Cgs would be modeled as a constant capacitance with voltage using a discrete, external capacitor. Cds would be modeled using a discrete, external diode. These three external components would be contained in the subcircuit.
In the EKV model, COX also affects the DC characteristics. But in practice, that effect is negligible, based on experiments using the Excel EKV model with the data from the 2SK1530.
The idea was to make the computed capacitances for the intrinsic device as low as possible. Then the vertical MOSFET will be modeled as a subcircuit with an external nonlinear gate-drain capacitance given by the same formula LTSpice uses for the Cgd in their proprietary VDMOS model. This would use a "Q=" formula for the nonlinear Q(v) of a discrete capacitor. Cgs would be modeled as a constant capacitance with voltage using a discrete, external capacitor. Cds would be modeled using a discrete, external diode. These three external components would be contained in the subcircuit.
In the EKV model, COX also affects the DC characteristics. But in practice, that effect is negligible, based on experiments using the Excel EKV model with the data from the 2SK1530.
I understand better now, however how is the intrinsic MOSFET going to work with such a small Cox? The MOSFET transconductance is proportional to Cox. Also, a MOSFET with such a small Cox will have a very poor subthreshold conduction slope. An external capacitor is of course not changing this.
You mentioned that your model has a low gain, could this be because of a low transconductance as above?
You mentioned that your model has a low gain, could this be because of a low transconductance as above?
andy_c said:
syn08 said:
I am not seeing a transconductance proportional to Cox. It is proportional to W and KP in the EKV model, and inversely proportional to L. I can adjust Cox in the spreadsheet and view the errors between simulated and measured DC data. The data doesn't change much at all.
I mentioned that the model shows an ON resistance that's too low (reciprocal of slope of Id vs. Vds in the triode region). The transconductance is OK. For a plot comparing the simulated and measured Id vs. Vgs with Vds=10V, see the graph in this post. That graph is also in the Excel file I posted here. When I change Cox, the graph doesn't change.
Oh, I see what's going on. I can adjust KP and COX independently. But using the physical equations, KP is related to COX by this:
KP = U0 * 1e-4*COX
See equation 14 in the EKV manual. Sorry for the confusion - I'm not a device physics guy, as you can probably tell.
KP = U0 * 1e-4*COX
See equation 14 in the EKV manual. Sorry for the confusion - I'm not a device physics guy, as you can probably tell
.
Re: MOSFET Noise models
Bob I stumbled onto this paper from Intusoft that has some mention of noise models for FETs (pg 223), for what it's worth:
http://www.waterlooengrgrp.com/downloads/modlist.pdf
Pete B.
Bob Cordell said:
Bob I stumbled onto this paper from Intusoft that has some mention of noise models for FETs (pg 223), for what it's worth:
http://www.waterlooengrgrp.com/downloads/modlist.pdf
Pete B.
Parameterize the Tricks for Spice Distortion Measurement
Link to make this easier to find:
http://www.diyaudio.com/forums/showthread.php?postid=1288439#post1288439
Link to make this easier to find:
http://www.diyaudio.com/forums/showthread.php?postid=1288439#post1288439
Edmond Stuart said:
Hi Edmond,
I'm back - with two dead computers. It seems the motherboard in my main machine has developed a problem that causes it to destroy whatever video card is put into it. I replaced the first bad video card with the card from my spare computer. That video card also died, leaving me with no working desktop machines. I'm typing this on my laptop until I get and install the new motherboard. So at present I have no music server, no simulation files, etc, until I get the main machine back up.
Regarding my Excel VBA code, I'm not doing anything with the registry explicitly. Maybe Excel does something behind the scenes here? In order to run the macro, I had to change the macro security of my Excel setup to "medium" from its default "high". With a "medium" setting, Excel prompts you as to whether you want to allow macros or not for each individual .xls file. It seems it will only allow them automatically on "high" security if one provides a certificate for the macro. But I don't know how to provide such a certificate. I think you can see the source code by doing an Alt-F11 after you open up the file, even though macros may be disabled. Then you can review it and see there is no registry manipulation at all - just numerical calculations. So I'm not sure what this software is objecting to, unless it's written to automatically reject Excel macros.
Distortion measurement and SPICE
I compared the results I can get, using the same models, with two different packages: PSPICE and LTSpice.
Even if I get absolutely the same results about idle currents, bias voltages, amplitudes, ..., I get very different results when I analyze the distortion on the output (by the Fourier analysis).
So ... who is telling (the better approximation of) the truth ?
Anybody, that compared simulation with measurement, can advice me about the "better" simulation package ?
Thanks
I compared the results I can get, using the same models, with two different packages: PSPICE and LTSpice.
Even if I get absolutely the same results about idle currents, bias voltages, amplitudes, ..., I get very different results when I analyze the distortion on the output (by the Fourier analysis).
So ... who is telling (the better approximation of) the truth ?
Anybody, that compared simulation with measurement, can advice me about the "better" simulation package ?
Thanks
