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Cronus - It's about time.

Hi Russ,

can you please explain the way to connect external clock to the Cronus?
There is a member who would use this oscillator with Cronus/Hermes (post #394)
http://www.diyaudio.com/forums/digi...phase-noise-jitter-crystal-oscillator-40.html

Thanks
Andrea

Russ, Brian,

sorry to ask again, could you please reply to my previous post? I would help the member who is asking how to implement external clocks in the Cronus board.
Or is there somewhere a schematic?

Thanks
Andrea
 
It's on the first page. :) There are SMA,uFL and DPI8/14 inputs for clocks. They must be 3.3V CMOS type clocks with ~50% duty cycle.

Ok, thanks, I have already seen the first page.
But how about the switching between the two oscillators?
Does the Cronus board provides the switching?
Is there any issue if the oscillators work both simultaneously, regardless of they are selected or not?

Thanks again
Andrea
 
Yes - Cronus does the switching based on the state of the CS(clock select) signal. The clock which is not selected sees a high impedance. The clock that is selected is used for the Hermes/DAC output and the re-clocking section.

I am working up a manual today that will go into more detail - but that should be enough info right there. :)

Thanks for the infos.
Waiting for the manual, the last question: you wrote "high impedance", so I suppose the two incoming clocks are not isolated by a multiplexer, a switch or so on.
Please, correct me if I was wrong.
I ask so because the oscillators to be implemented is a standard oscillator, without any "enable" pin (like Crystek), so they oscillate anyway, also if they are not selected to operate. There is the option to power off the oscillator not selected, but the slicer is powered on in any case, so they provide low or high logic levels, but not high impedance.
Is this an issue?

Thanks
Andrea
 
Thanks, have just ordered 45/49 Rheas, plus 2 blank Rheas to compare against 22/24 NDK clocks at a later stage.

You can use 5 x 7 clock and the larger Crystek CCHD-9xxxx clocks as well as the small NDK types. There is a spot for optional (some clocks may need it) local bypass cap on top and on the bottom.
The NDK datasheet says I need 0.01 uF bypass cap. Can anyone recommend a particular cap for the Rhea board?
 
Hi,
What is the recommended powersupply spec for these modules? I can see in the first post that the Cronus has a maximum current of 800mA. Is that included powering the BBB and Hermes?

800ma is the very max the cronus reg can handle. :)

I power my Cronus/Hermes from the digital supply of the target DAC.

In practice (in my setup) I am seeing < 200 ma current draw.
 
You are talking about two different approaches to the same sort of desired result.

Using a FIFO is a buffer approach which is good where time domains do not match - but you have to introduce a delay - and there is the chance of buffer over-runs and under-runs which can be tricky to deal with.

Cronus is a different approach where the source and the reclocking are done with exactly the same clock and same time base. So no buffering is required - the digital stream arrives from the cronus already perfectly time aligned with no chance for data loss and no change in time domains.

The key is this - in order to isolate a signal most isolators use a high frequency modulator - this changes the time domain of the signals to that of the modulator. What cronus does is make sure that at the output the signals are again brought back into exact phase alignment with the master clock.

So the effect is you get the nice clean signal of a clocked FIFO - without any need for a FIFO because the source is using the exact time base as the output. It is only when you mix clock domains that you need use a FIFO.

They are two very different ways to achieve the same desired result - which is a jitter free digital source.

Cheers!
Russ
 
Here are the conus dimensions for planning:
 

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