Very nice explanation Sandro - thank you for sharing.
My understanding is that with cascodes, because they isolate the amplifier Miller capacitance by holding the Base<>collector voltage constant on the lower amplifying device, you get high bandwidths since there is no capacitive feedback in this regime. However, when I have used cascodes in the VAS position, I have noticed serious problems if the cascode is driven into saturation with sticking - all sorts of effort required to limit excess base charge injection. Can you go through the cascode delay issue you mention and what the mechanism is?
BTW I ditched cascoded VAS ages ago - a simple helper transistor get me to ppm distortion levels at 20 kHz and its and elegant and clean IMV which are design criteria I tend to like
Last edited:
BTW I ditched cascoded VAS ages ago - a simple helper transistor get me to ppm distortion levels at 20 kHz and its and elegant and clean IMV which are design criteria I tend to like
What is "helper transistor"?
@Bonsai:
Hi Andrew, no problem.
The delay mechanism is purely capacitive loading.
Say you have a cascode transistor Q1 and you feed a current into the emitter. This current could come from a Common emitter, a current mirror, etc.
Now, the current has 2 paths, 1. it goes into the internal transistor emitter, 2. it goes into Cpi. For the former, it will make it out of the collector, for the latter, it will come out from the base. The more current signal goes out the base, the more signal loss you get. [Note: I think the internal transistor as an ideal transistor with no capacitances, that is my mental model]
The current into the emitter will ratio following a simple current divider between the incremental impedance of the emitter 're' = 1/GM or Cpi. The -3dB frequency, when the current splits evenly is 1/(re*Cpi* 2*pi).
Many prefer to think of this delay in terms of 'tau_f', the forward base transit-time of the transistor, which is the time a carrier takes to cross the base region. Hence, there is a delay of tau_f for a current that goes into the emitter to come out of the collector. In practice, it is the same thing that I decribed above since Cpi = gm*tau_f.
So what happens when the cascode transistor saturates? Well tau_f skyrockets. If you are into device physics, this is due to the slope of the base charge profile decreasing dramatically which causes increased time for a carrier to traverse the base. So what ends-up happening is that Cpi skyrockets too. To make matters worse, the CB junction forward biases and Cmu (CJC) also skyrockets. Finally, beta crashes too. As a result, lots of bad things happen including:
- Driving the minor loop unstable
- The base current of the cascode can be large enough to bring down its VBIAS at its base, which in turn can saturate the common emitter feeding its base and therefore create more problems
- Stuff I have not though about... saturation of a BJT is just bad business.
There are things you can do, but all require many transistors to implement. These include active clamps which reach back to input stage to prevent the second stage from going further into saturation, and very low impedance, complementary VBIAS generators. In discrete design neither is atractive due to board area and cost. In an op-amp, where transistors are free, it is not a big deal [Resistors are more problematic since they take a lot more chip area].
Well, that's it. Many think of the cascode as an innocent circuit, but care is needed too.
- Gives you an extra Beta
- Does not rob you of head room in the second stage
- Easy to by-pass (just a cap) if you need to.
@Shaun: Hi Shaun, The helper transistor is the Emitter follower in the second stage. In the Honey badger amplifier it is Q9.
https://cdn.shopify.com/s/files/1/1006/5046/files/P-DIYAB-2V20-diyAB-amp-schematic.pdf
Best, Sandro
Hi Andrew, no problem.
The delay mechanism is purely capacitive loading.
Say you have a cascode transistor Q1 and you feed a current into the emitter. This current could come from a Common emitter, a current mirror, etc.
Now, the current has 2 paths, 1. it goes into the internal transistor emitter, 2. it goes into Cpi. For the former, it will make it out of the collector, for the latter, it will come out from the base. The more current signal goes out the base, the more signal loss you get. [Note: I think the internal transistor as an ideal transistor with no capacitances, that is my mental model]
The current into the emitter will ratio following a simple current divider between the incremental impedance of the emitter 're' = 1/GM or Cpi. The -3dB frequency, when the current splits evenly is 1/(re*Cpi* 2*pi).
Many prefer to think of this delay in terms of 'tau_f', the forward base transit-time of the transistor, which is the time a carrier takes to cross the base region. Hence, there is a delay of tau_f for a current that goes into the emitter to come out of the collector. In practice, it is the same thing that I decribed above since Cpi = gm*tau_f.
So what happens when the cascode transistor saturates? Well tau_f skyrockets. If you are into device physics, this is due to the slope of the base charge profile decreasing dramatically which causes increased time for a carrier to traverse the base. So what ends-up happening is that Cpi skyrockets too. To make matters worse, the CB junction forward biases and Cmu (CJC) also skyrockets. Finally, beta crashes too. As a result, lots of bad things happen including:
- Driving the minor loop unstable
- The base current of the cascode can be large enough to bring down its VBIAS at its base, which in turn can saturate the common emitter feeding its base and therefore create more problems
- Stuff I have not though about... saturation of a BJT is just bad business.
There are things you can do, but all require many transistors to implement. These include active clamps which reach back to input stage to prevent the second stage from going further into saturation, and very low impedance, complementary VBIAS generators. In discrete design neither is atractive due to board area and cost. In an op-amp, where transistors are free, it is not a big deal [Resistors are more problematic since they take a lot more chip area].
Well, that's it. Many think of the cascode as an innocent circuit, but care is needed too.
I agree. The emitter follower is easier to work with, and has extra perks over the cascode including:
- Gives you an extra Beta
- Does not rob you of head room in the second stage
- Easy to by-pass (just a cap) if you need to.
@Shaun: Hi Shaun, The helper transistor is the Emitter follower in the second stage. In the Honey badger amplifier it is Q9.
https://cdn.shopify.com/s/files/1/1006/5046/files/P-DIYAB-2V20-diyAB-amp-schematic.pdf
Best, Sandro
Last edited:
5.2. Audio Amplifier Design Fundamentals: Measuring harmonic distortion in LTSpice 1
Hi all, just to let you know that I just uploaded the next video of the series:
5.2. Audio Amplifier Design Fundamentals: Measuring harmonic distortion in LTSpice - Part 1
SW-VFA-01 Video 5.2 Part 1
The video covers the fundamentals of measuring distortion in LTSpice. The next video, part 2, will be a demo.
I'll be uploading the demo video tomorrow.
Also, not a huge ask, to all watching, pretty please, hit the subscribe button.
Enjoy!
Hi all, just to let you know that I just uploaded the next video of the series:
5.2. Audio Amplifier Design Fundamentals: Measuring harmonic distortion in LTSpice - Part 1
SW-VFA-01 Video 5.2 Part 1
The video covers the fundamentals of measuring distortion in LTSpice. The next video, part 2, will be a demo.
I'll be uploading the demo video tomorrow.
Also, not a huge ask, to all watching, pretty please, hit the subscribe button.
Enjoy!
5.2. Audio Amplifier Design Fundamentals: Measuring harmonic distortion in LTSpice 2
Hi all, just to let you know that I just uploaded the next video of the series, part 2 of the How to measure distortion in LTSpice video:
5.2. Audio Amplifier Design Fundamentals: Measuring harmonic distortion in LTSpice - Part 2
SW-VFA-01 Video 5.2 Part 2
In this video I do a demonstration of how to measure harmonic distortion in LTSpice.
Next video will be about distortion in resistors.
Again, not a huge ask, to all watching, pretty please, hit the subscribe button.
Enjoy!
Hi all, just to let you know that I just uploaded the next video of the series, part 2 of the How to measure distortion in LTSpice video:
5.2. Audio Amplifier Design Fundamentals: Measuring harmonic distortion in LTSpice - Part 2
SW-VFA-01 Video 5.2 Part 2
In this video I do a demonstration of how to measure harmonic distortion in LTSpice.
Next video will be about distortion in resistors.
Again, not a huge ask, to all watching, pretty please, hit the subscribe button.
Enjoy!
That is true... while it is no Spectre, LTSpice is not bad at all and quite adequate for our needs.
Spectre Simulation Platform
Spectre Simulation Platform
I've been following (and subscribed) for a little while now, and this last set of videos has for me at least been the most useful yet. I've come across various sets of recommended parameters for best simulation in LTSpice but always sporadically and only occasionally with explanations (although I think I skipped that part in Cordell to get to creating BJT models...). This was clear, concise, and complete. This is shaping up to be the equivalent of a multi-term class on audio amplifiers, without the hangovers. Really nice work!
Same story on your clear explication of the drawbacks of cascodes--I've seen some of these things hinted at and partially mentioned here and there but never a full and clear layout of the issues and causes.
A few questions for clarification: Based on the equations you presented, am I correct in saying the absolute level of emitter current is essentially irrelevant to the Cpi, Re voltage divider action, since both impedances scale with 1/gm? Do these issues arise only when in "hard saturation" or do they also begin to show up as the transistor approaches saturation ("quasi saturation" region)? If they do arise as VCB declines, should these issues also be considered on the input side of current mirrors? And are issues worse with high breakdown transistors?
Same story on your clear explication of the drawbacks of cascodes--I've seen some of these things hinted at and partially mentioned here and there but never a full and clear layout of the issues and causes.
A few questions for clarification: Based on the equations you presented, am I correct in saying the absolute level of emitter current is essentially irrelevant to the Cpi, Re voltage divider action, since both impedances scale with 1/gm? Do these issues arise only when in "hard saturation" or do they also begin to show up as the transistor approaches saturation ("quasi saturation" region)? If they do arise as VCB declines, should these issues also be considered on the input side of current mirrors? And are issues worse with high breakdown transistors?
Hi Dk,
Thanks! Happy to hear you are finding them useful.
To your questions:
Based on the equations you presented, am I correct in saying the absolute level of emitter current is essentially irrelevant to the Cpi, Re voltage divider action, since both impedances scale with 1/gm
Yes for the diffusion component of C_PI = gm*tf
C_PI actually has two components = gm*tf + CJE where the second term is the depletion capacitance which is independent of IC and hence the associated time constant (CJE/gm) goes down with IC.
Sorry for not including the CJE component
Do these issues arise only when in "hard saturation" or do they also begin to show up as the transistor approaches saturation ("quasi saturation" region)?
- They also begin to show up as the transistor approaches saturation.
If they do arise as VCB declines, should these issues also be considered on the input side of current mirrors?
- These issues also be considered on the input side of current mirrors. That is why, unless the output transistor of the current mirror see high voltage, you are better off using LV transistors. LV transistors are much better at handling saturation and quasi-saturation.
And are issues worse with high breakdown transistors?
- What do you mean with high breakdown? High BV_CEO? If yes, then yes. High BV_CEO in a transistors results is worse performance at low VCE.
Thanks! Happy to hear you are finding them useful.
To your questions:
Based on the equations you presented, am I correct in saying the absolute level of emitter current is essentially irrelevant to the Cpi, Re voltage divider action, since both impedances scale with 1/gm
Yes for the diffusion component of C_PI = gm*tf
C_PI actually has two components = gm*tf + CJE where the second term is the depletion capacitance which is independent of IC and hence the associated time constant (CJE/gm) goes down with IC.
Sorry for not including the CJE component
Do these issues arise only when in "hard saturation" or do they also begin to show up as the transistor approaches saturation ("quasi saturation" region)?
- They also begin to show up as the transistor approaches saturation.
If they do arise as VCB declines, should these issues also be considered on the input side of current mirrors?
- These issues also be considered on the input side of current mirrors. That is why, unless the output transistor of the current mirror see high voltage, you are better off using LV transistors. LV transistors are much better at handling saturation and quasi-saturation.
And are issues worse with high breakdown transistors?
- What do you mean with high breakdown? High BV_CEO? If yes, then yes. High BV_CEO in a transistors results is worse performance at low VCE.
Thanks! The idea that I had in mind when I started this was to combine:
- Theory presented in a visual way than say in a book, hence my choice of Power point as a presentation vehicle
- The design of a top-of-the-line amplifier showing all the tricks I know... the bulk of this is yet to come
- Simulation using LTSpice, I strongly believe in the idea of "design it in simulation and then build it" concept, plus, there is a lot to learn via simulation
So far the formula is working... I think.
With some help, I would like to add a lab component to the series. I can't do it myself since I don't even have a scope (I leveraged all the equipment from ADI when I lived in Boston). So Stuart has volunteered to help me on that front.
Anyway, thanks again!