D-Noizator: a magic active noise canceller to retrofit & upgrade any 317-based V.Reg.

Then, do not present an add on module in a misleading way.

This really seems to be a language issue since I have not mislead but you seem to have misunderstood.

Anyhow an add-on module which can be directly soldered in place of an existing component is a much better solution both mechanically and electrically than e.g. hanging it using wires. That is how I will implement this. You can do whatever you prefer.
 
Back to serious work, referring to post 1040.

My simulations of the PSU does show that the capacitive loading is critical about stability.
I know the gap between simulations and realities.
I doubt it is a simulation artifact, I think it is a reality inherent to the topology.

From posts early in this thread, it was extensively discussed since June 11, 2020, about oscillations that could occur depending of the ESR of a 100 uF output capacitor.
My simulations, agree, there is a sweet range of ESR values for stable operation.
This is a serious issue, because a PSU stability that depends on loading is pretty annoying, if not unacceptable.
Electrolytic caps don't have the reputation for stable characteristics over time. Such a PSU can be a time bomb.
So, the great PSRR potentially obtainable with this topology is burdened by this trouble. There is no free lunch.
Please comment about observed oscillations related to the output capacitor.
 
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I wouldn’t build actual regulator without output capacitor. However, I don’t see any problems with circuit stability over time (maybe with 50 or so years of usage).

Output capacitor will be Panasonic FC series with 5.000 – 10.000 hours lifetime at the max. rated temperature. At expected 40 to 50 °C that becomes 100.000 working hours minimum for datasheet declared performance decrease. How long do you intend to live? :)

This regulator will be connected, to the circuit it supplies, with some wire and that introduces inductance (5 – 10 nH per cm) which isolates any load capacitance from affecting regulator stability.
So, don’t worry be happy :sing:
 
TL431 datasheet has diagrams displaying the stability boundary conditions regarding capacitive loads. According to simulations using 100u as output capacitor should be stable for both TL431 series and shunt regulators with denoisers. Output capacitor ESR does not seem to be an issue. However low ESR should improve high frequency performance.
 
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How come, there is a bunch of posts in this thread reporting oscillation troubles related to the output capacitor ?

Admit, you were skipping homework (posts reading), otherwise you would know the answer. :devilr:

It was not determined, at the beginning, that there is a sweet spot for the output capacitor ESR. Some instability was also due suboptimal designs.
For instance, my version of regulator appears to be rock stable and there was no way for me to introduce any instability.
 
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Up to #950 is enough. There is nothing new about instability after that point.

It is OK that instability appears in your simulation as it does in mine as well. I described what combination is stable for me. For you, it could be slightly different but should be the same in general.
Build the test circuit with what you simulation confirms as stable.
 
It is OK that instability appears in your simulation as it does in mine as well.

It seems that my comment regarding the stability of TL431+denoiser was not correct. I'm not sure which is the latest series regulator but at least the circuit in post #1040 is unstable if output capacitor ESR is too low (under 15 mOhm) even without C1.
 
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We deal with a double loop system.
Without denoising, whatever used regulating technique, it is a loop with stability issues of it's own asking for a compensation if not taken care internally in IC regulators
Adding the denoiser makes it double loop.
Asking for compensation, here C4 R7 22nF 33ohm. An alternative is an inductance at the emitter of the denoiser transistor.
This double loop is a pretty much involved system, difficult to compensate by trial and errors. Time constants ( poles and zeros ) of the two loops interact each other.
 
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Output phase is both affected by R7/C4 and output capacitor ESR. It’s the same as was with LM317 + Denoiser or Dienoiser.
Very stable conditions are with C4 100 nF, R7 22 Ω. With those values, regulator is stable for output capacitor ESR in the range from 5 mΩ to kiloohms or no output capacitor at all. There is no need to ask for more stable conditions.
 
I do not have as good.
With 100nF 22 I have stable for output cap ESR < 2.
With 22nF 33 I have stable for < 0.6 ohm

Some change about PSRR.

The simulation seems sensible to transistor models.
Transistors I use are the LTSpice default.
I do not have a good model for ZTX951, and none for 2N3019.

With C4 100nVF R7 0.2ohm it is stable with no output cap
 
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I have no difference between ZTX and BC, except for the noise density. Here is ZTX model I use:

*ZETEX ZTX951 Spice model Last revision 27/5/92
*
.MODEL ZTX951 PNP IS=1.3766E-12 NF=1.013 BF=187 IKF=5.0 VAF=66.3
+ISE=1.4E-13 NE=1.41 NR=1.0099 BR=56 IKR=0.9 VAR=33 ISC=1.7E-12
+NC=1.4 RB=0.029 RE=0.020 RC=0.0255 CJC=287E-12 MJC=0.4522
+VJC=0.4956 CJE=1.15E-9 TF=0.83E-9 TR=20E-9
*
*$
*

You’l have to edit asc file in some text editor to replace BC with ZTX.