Don't worry about the capacitance. It's a complete non-issue for your specific setup.
Edit: I used jfets with idss of around 10mA
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I don't think anyone here is going to use 1.41 Ohm source resistors (possibly 1 Ohm but not 1.41 Ohm).
But the information you provided is useful/interesting.
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Yes I understand Patrick. However people don't increase source resistance proportionally when parralleling mosfets.
Do you see Nelsons amps with 10 Ohm source resistors?
How is an assumption of extremely high source resistances or unrealistic bias currents relevant to an actual amplifier?
There is no language barrier, it's an issue of application. This discussion is about amplifiers we build. Using a bias current of 2A for the whole amp, and 0.47 ohm - or any combination of values, pick one - the voltage drop across 'n' pairs will be 1/n that of a single pair.
There is no language barrier, it's an issue of application. This discussion is about amplifiers we build. Using a bias current of 2A for the whole amp, and 0.47 ohm - or any combination of values, pick one - the voltage drop across 'n' pairs will be 1/n that of a single pair.
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Borbely disagrees.
He states in some of his power amplifier articles that the minimum bias for a FET output stage be set to at least 500mA, irrespective of how many device pairs are used.
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The F5 and F5t and F5x are all push/pull ClassAB power amplifiers.
If you use a load that never draws more peak transient current than double the output stage bias current, then the push/pull output stage remains in ClassA.
Exceed that maximum ClassA current and all these F5 variants transition into ClassB
It's this ability to deliver more current into demanding loadings that makes these amplifiers so good. Just like so many other push/pull topologies that are properly designed.
Andrew. that depends on the bias current. we have had this discussion before. no need to repeat that.
you can do the Math and tell me when my F5 goes in to class A/B.
with +/-24V rails and 2.5A bias.
All high bias (Class A at full voltage swing at 8 ohm) push pull amps are classified as class A.
you can do the Math and tell me when my F5 goes in to class A/B.
with +/-24V rails and 2.5A bias.
All high bias (Class A at full voltage swing at 8 ohm) push pull amps are classified as class A.
Yes 2.5A should be good, maybe goes to AB if you have speakers with low impedance dips and use it at high power...
Let me see if I can make this clearer with the following example:
Instead of the 2SK1530, let's use the F5 transistor FQA19n20c, which was
the original device, and for simplicity let's use 0.5 ohm Source resistors.
At the temperatures we anticipate, it has a Vgs of about 2.9V at 1 amp,
and about 2V at .5 amp.
The transconductance at 1A is about 4.5 S, or the equivalent resistance of
0.22 ohms. If we add 0.5 ohms resistor on the Source, the equivalent
resistance becomes .722 ohms, and the inverse of this is the "new"
transconductance figure of 1.38 S (amps/volt). The Gate voltage required
to produce a 1 amp current is 2.9V + .5V = 3.4 V DC
The transconductance at 0.5A is about 3.2 S, or the equivalent resistance of
0.31 ohms, and adding 0.5 ohms makes it .81 ohms, or 1.23 S. The Gate
voltage required to product this is 2.0V + .25 = 2.25V
So, if we parallel two transistors at 0.5 amp bias, with one transistor at 1A,
we get equivalent transconductance of 1.23*2 = 2.46 S vs 1.38 S, a
ratio of about 1.8 higher.
If we were running this as a follower output stage, then we would be done,
but Patrick is considering the value of the Gate-to-supply resistors in the F5,
(given the same DC current from the input devices) and sees that the
open loop gain would be adjusted not only by the transconductance of the
output stage but also the values of those resistors, so the open loop is
higher by 1.8 times 2.25V/3.4V. The result is 1.8 * 2.25 / 3.4 = 1.19
times higher for the case of two parallel devices.
Capacitance will add up as the square root of parallel devices for Cgs, the
Gate to Source capacitance, and as a straight sum for Cgd, the Gate to
Drain capacitance.
I'm sure you will let me know if I've made any errors...
Instead of the 2SK1530, let's use the F5 transistor FQA19n20c, which was
the original device, and for simplicity let's use 0.5 ohm Source resistors.
At the temperatures we anticipate, it has a Vgs of about 2.9V at 1 amp,
and about 2V at .5 amp.
The transconductance at 1A is about 4.5 S, or the equivalent resistance of
0.22 ohms. If we add 0.5 ohms resistor on the Source, the equivalent
resistance becomes .722 ohms, and the inverse of this is the "new"
transconductance figure of 1.38 S (amps/volt). The Gate voltage required
to produce a 1 amp current is 2.9V + .5V = 3.4 V DC
The transconductance at 0.5A is about 3.2 S, or the equivalent resistance of
0.31 ohms, and adding 0.5 ohms makes it .81 ohms, or 1.23 S. The Gate
voltage required to product this is 2.0V + .25 = 2.25V
So, if we parallel two transistors at 0.5 amp bias, with one transistor at 1A,
we get equivalent transconductance of 1.23*2 = 2.46 S vs 1.38 S, a
ratio of about 1.8 higher.
If we were running this as a follower output stage, then we would be done,
but Patrick is considering the value of the Gate-to-supply resistors in the F5,
(given the same DC current from the input devices) and sees that the
open loop gain would be adjusted not only by the transconductance of the
output stage but also the values of those resistors, so the open loop is
higher by 1.8 times 2.25V/3.4V. The result is 1.8 * 2.25 / 3.4 = 1.19
times higher for the case of two parallel devices.
Capacitance will add up as the square root of parallel devices for Cgs, the
Gate to Source capacitance, and as a straight sum for Cgd, the Gate to
Drain capacitance.
I'm sure you will let me know if I've made any errors...
Nelson,
I would consider it a fairer comparison if you use 2x MOSFET in parallel with 0.5R source degeneration, vs. 1x MOSFET with 0.25R source degeneration.
That way you are comparing apple to apple, IMHO.
Afterall, you don't need current balancing resistors with one MOSFET on ist own.
Patrick
I would consider it a fairer comparison if you use 2x MOSFET in parallel with 0.5R source degeneration, vs. 1x MOSFET with 0.25R source degeneration.
That way you are comparing apple to apple, IMHO.
Afterall, you don't need current balancing resistors with one MOSFET on ist own.
Patrick
None of us would never do that so we disagree.
If I'm going go use 0.25 on a single pair I'll still use 0.25 on 3 pairs, and match appropriately.
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For a text book comparison your suggestion is probably fair, but none of us here live in that text book.
Thanks Mr. Pass, that clears things up quite a bit and gives a basis for people to arrive at their own implementations. I hadn't even thought about gate to supply resistor causing a reduction in gain. Definitely makes some things clear.
If you don't mind, I have a follow-up question.
The F5Turbo document illustrates use of a fourth pair with additional changes in the front end. Is it feasible for that front end to hanlde the capacitance of four gates, nearly 3.5 nF?
I would think that to be quite the loss to the discussion.
I definitely think that 0.25 and 0.5 are realistic values for a one pair versus two pair comparison. But if you added a third pair, would you compare it by upping the sister value to 0.75 ohm? Or would you change the one pair value to 0.19 ohm?
I think what the original poster and all of us are trying to work out is that whether adding more pairs without changing the bias - or much else - has any benefits. From what I understand you are saying that there isn't much to gain. We're trying to understand why. That's all.
Patrick, I'd say more than 90% of the people who've built the one pair version have used 0.5 ohm source resistors. It would be much more practical and consistent to use this as the one pair basis like Mr. Pass has drawn out. After all, most users not as advanced as you would be working off the published document and schematics directly,
If you don't mind, I have a follow-up question.
The F5Turbo document illustrates use of a fourth pair with additional changes in the front end. Is it feasible for that front end to hanlde the capacitance of four gates, nearly 3.5 nF?
I would think that to be quite the loss to the discussion.
I definitely think that 0.25 and 0.5 are realistic values for a one pair versus two pair comparison. But if you added a third pair, would you compare it by upping the sister value to 0.75 ohm? Or would you change the one pair value to 0.19 ohm?
I think what the original poster and all of us are trying to work out is that whether adding more pairs without changing the bias - or much else - has any benefits. From what I understand you are saying that there isn't much to gain. We're trying to understand why. That's all.
Patrick, I'd say more than 90% of the people who've built the one pair version have used 0.5 ohm source resistors. It would be much more practical and consistent to use this as the one pair basis like Mr. Pass has drawn out. After all, most users not as advanced as you would be working off the published document and schematics directly,
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