andrea_mori,
I've been using an adaptation of the Matthys / Driscoll oscillator circuit for many years now, in fact my first post on DiYAudio back in 2004 was inquiring about "100MHz" clock circuit designs IIRC
I've recently had a "second look" at the Mattys implementation for a "Closed Group sponsored" DAC project I've been working on for far to long now, and with almost two decades or so of "extra" experience appreciate some simple methods to improve circuit performance - especially WRT close in phase noise.
(Without having to read trough this whole thread) Did you ever get a 90MHz - 100MHz transistor version working correctly?, I know you had too little gain with the JFET version for 50MHz+ operation....
One area that was initially surprising (although not really) is that the circuit is VERY keen to have spurious oscillations above 1-2GHz (typically about 2.5GHz superimposed on the "100MHz" wanted oscillation...
Normally I use a 500MHz analogue scope with 1.5GHz active probes on the bench, and the waveform look reasonably clean, however looking more closely one could see ripples on the 100MHz waveform that appear very apparently on a higher speed scope (digital I'm afraid) which turned out to be the parasitic 2.5GHz oscillation... The 500MHz scope acted as a nice filter - nice "clean" Signwaves... You would think (but again not surprising) that 500MHz B/W would be enough... and that "500MHz B/W" is Tektronix "500MHz" so add atleast an extra 100MHz to 200MHz B/W for tolerance!!!
I found that its VERY hard to tame these GHz oscillations on the standard Matthys circuit - and recently I searched for the original Healey / Driscoll Patent (Sept 17 1974, Pat# 3,836,873) and noticed with a "Smile" that they used Ferrite beads to tame these all too inevitable parasitic oscillations...
Also, the Healey / Driscoll circuit has the potential for far better close in Phase noise, something that Matthys seems to have missed (overlooked) when he "Simplified" the design.
It be good to compare design notes if your interested
What would be really interesting would be to see if your PCB's displays any sign of the 2GHz+ oscillations... It be great to have a PCB to measure and see if I can apply some simple mods to improve performance (if possible) ....
BTW. Well done with your new design - I suspect that your 1Hz PN will dramatically improve with thermal control / thermal shielding as at this Close-in LF frequency your looking more at "Wonder / frequency drift" rather then "pure" PN due to the XO circuit itself... (if you understand what I'm trying to say here)...
Sonically, its my experience that this LF frequency drift / Wonder impacts the "L/R sound stage" in a manor far greater then one would first expect...
I've been using an adaptation of the Matthys / Driscoll oscillator circuit for many years now, in fact my first post on DiYAudio back in 2004 was inquiring about "100MHz" clock circuit designs IIRC
I've recently had a "second look" at the Mattys implementation for a "Closed Group sponsored" DAC project I've been working on for far to long now, and with almost two decades or so of "extra" experience
appreciate some simple methods to improve circuit performance - especially WRT close in phase noise.(Without having to read trough this whole thread) Did you ever get a 90MHz - 100MHz transistor version working correctly?, I know you had too little gain with the JFET version for 50MHz+ operation....
One area that was initially surprising (although not really) is that the circuit is VERY keen to have spurious oscillations above 1-2GHz (typically about 2.5GHz superimposed on the "100MHz" wanted oscillation...
Normally I use a 500MHz analogue scope with 1.5GHz active probes on the bench, and the waveform look reasonably clean, however looking more closely one could see ripples on the 100MHz waveform that appear very apparently on a higher speed scope (digital I'm afraid) which turned out to be the parasitic 2.5GHz oscillation... The 500MHz scope acted as a nice filter
- nice "clean" Signwaves... You would think (but again not surprising) that 500MHz B/W would be enough... and that "500MHz B/W" is Tektronix "500MHz" so add atleast an extra 100MHz to 200MHz B/W for tolerance!!!I found that its VERY hard to tame these GHz oscillations on the standard Matthys circuit - and recently I searched for the original Healey / Driscoll Patent (Sept 17 1974, Pat# 3,836,873) and noticed with a "Smile" that they used Ferrite beads to tame these all too inevitable parasitic oscillations...
Also, the Healey / Driscoll circuit has the potential for far better close in Phase noise, something that Matthys seems to have missed (overlooked) when he "Simplified" the design.
It be good to compare design notes if your interested
What would be really interesting would be to see if your PCB's displays any sign of the 2GHz+ oscillations... It be great to have a PCB to measure and see if I can apply some simple mods to improve performance (if possible)
....BTW. Well done with your new design - I suspect that your 1Hz PN will dramatically improve with thermal control / thermal shielding as at this Close-in LF frequency your looking more at "Wonder / frequency drift" rather then "pure" PN due to the XO circuit itself... (if you understand what I'm trying to say here)...
Sonically, its my experience that this LF frequency drift / Wonder impacts the "L/R sound stage" in a manor far greater then one would first expect...
Last edited:
@ JohnW, Hi
For the non specialist as I, what do you mean by thermal shielding related to thr temperature drift please? Is it about oven and crystal in between exchanges to avoid temperature drift when the best theoric temperature is reached or is it about external temperaturs changes due to external heat and cold (i.e. temperature moves due to the whole dac and powersupplies because of temperature room changes, difference between 19 and 23 degrees due to seasons for instance)? So is it about to do a little case around the oven to avoid drift? Or anythingelse ?
For the non specialist as I, what do you mean by thermal shielding related to thr temperature drift please? Is it about oven and crystal in between exchanges to avoid temperature drift when the best theoric temperature is reached or is it about external temperaturs changes due to external heat and cold (i.e. temperature moves due to the whole dac and powersupplies because of temperature room changes, difference between 19 and 23 degrees due to seasons for instance)? So is it about to do a little case around the oven to avoid drift? Or anythingelse ?
Last edited:
Not sure where to start with answering your questions
A DAC /ADC has three basic "Input nodes" what will result in a change of "Output":-
1. Data / Audio input
2. PSU / Reference / Ground noise
3. Clock
The first 2 are easier for audio engineers to manage - measuring clock Phase noise with the precision and at the LF B/W required for audio systems is VERY hard / expensive / time consuming..
Our consideration with audio is not absolute clock accuracy (the absolute clock frequency) - but precision (that this frequency does not change over the short term, I'm thinking over 10's of seconds and better if possible).
So within reason we dont care about the actual frequency, but just that this frequency is stable and does not drift / wonder about "too much"- any "effect / action" that causes a change in temperature will result in a clock frequency shift...
Both the Crystal itself AND oscillator circuit will be effected by temperature... and they will be effected differently.
As we just want to stop the frequency changing / drifting (presuming our PSU is ROCK steady, clean / no noise), we just need to insure there is no temperature variation over time, so any methods that can be taken to slow / control the temperature change of the Crystal / XO circuit will directly impact the resultant frequency drift.
So simple actions such as thermally insulting the crystal and XO circuit from "unwanted" heat sources/ drafts will be directly beneficial. The rate and change of temperature change will be directly observed on the frequency output - so an audio engineer can take the following "Blind action" tasks to "presume" a low phase noise output.
1. Any noise on the PSU will be seen DIRECTLY on the clock output, so apply best audio engineering practices (+ consider that the circuit needs to be decoupled at its operating frequency and above!!!) for lowest PSU noise.
2. Consider the circuit impedance, for lowest noise in Audio you would never use 100k resistors in the direct signal path - an XO circuit is just an "unstable" amplifier (Gain block) so the same design tricks for lowest phase noise apply as when we want to design a Phonostage with the lowest noise (highest S/N ratio)... However some / many XO circuit nodes require the highest impedance for highest in circuit Q / lowest circuit loading and this is the challenge to the designer....
3. Temperature stabilization - you can 100% count that the rate of change in temperature will be DIRECTLY observed on the clock output!
4. Once transitioning into the digital realm, fastest edges = shortest period in a Logic "undetermined" state = lowest additive Jitter...
"Common sense" temperature management will reap direct benefits- keep any temperature gradient to the minimum......
We have a couple of Wavecreast Phase noise systems in the lab, and they sound like demented vacuum cleaners when they are powered - with huge full width blower fans to keep the temperature "stable" across the internal PCB's...
Last edited:
No problem
, and thank you for teaching the meaning of "pedagogy" (which I had to Google) - My English is not the best!
Last edited:
The reason for the SC cut crystal is the stability across a temperature range. It's a broader range than an AT crystal but it around 50C I think. A good oven and you get very good stability. At the right range it's less sensitive to temperature.
At the other extreme there are crystal thermometers which use the term sensitivity to measure temperature. You do not want to be building one of these unintentionally.
The Wavecrest is quite good with I think a 2 ps one shot resolution. You can also get PP jitter which may be more meaningful.
However if jitter not managed throughout the DAC or ADC it may be meaningless.
At the other extreme there are crystal thermometers which use the term sensitivity to measure temperature. You do not want to be building one of these unintentionally.
The Wavecrest is quite good with I think a 2 ps one shot resolution. You can also get PP jitter which may be more meaningful.
However if jitter not managed throughout the DAC or ADC it may be meaningless.
By the Leeson equation when temperature increases also the phase noise close to the carrier increases. The plot published in the previous posts have been measured at room temperature with sc-cut crystals. We will measure both oscillators with a suitable oven to get the crystal at the temp specified in the datasheet (around 85 degrees C)
I have a couple of the Wavecreast SIA4000 systems in the lab not the earlier DTS2077 "Frequency counter" type units I believe your thinking off...
The SIA4000 are very different beasts to the DTS units with a nice LF modulation tool, and I quote from the spec sheet:-
"The Low Frequency Modulation tool provides the capability of measuring low frequency (<100 kHz) periodic components on a carrier. Plot 3 shows the spectral view of jitter over 1 clock period
from 0 Hz to 10 kHz of a 2 GHz sinewave modulated with a 100 Hz peak deviation 1 kHz sinewave. The 1 kHz spectral component has a magnitude of 25 as and the background noise is <1 as.
NOTE: 1 attosecond (as) equals 10-18 sec."
I can attest to the fact that the LF NF is well below 1 attosecond ....
WRT SC cut...
I've avoided SC cut as I achieve better Close in phase noise from AT cut Xtals at the higher clock frequencies I work with, as you say I believe SC cut is better for Absolute "temperature compensated" accuracy rather then lowest Phase noise.
AT cut typically has x3 lower ESR then SC cut, with Ultra LN XO's designs the thermal noise of this ESR becomes the dominate factor.
Another problem with SC cuts is the very close spurie resonate modes that need to Notched out, these extra notch circuits add noise... Circuits without these notches can be observed to "Jump frequency" on alternative power up cycles...
Also, is SC cut now available in 90MHz+ range???, when I looked many years back they where designed for 10MHz type applications... maybe I'm well behind the curve now, but a doubt the biggest issues of ESR can be resolved with this cut...
The in-circuit Q of an overtone (3rd or 5th) AT cut can be well over 100K... at higher currents its possible to achieve a working Q of over 90% of the Crystals intrinsic Q with the Healey / Driscoll type circuit - a circuit where the lowest Crystal ESR factors heavily close in offset PN.
At such close in Frequency offsets, its a challenge to know exactly what your looking at - are you observing the frequency Drift of the resonant element, or the residual XO "Gain block noise" - text books always show nice obvious changes in the slope order on their graphs - but IME its really not so obvious at such tight offset...
Its a battle between between in-circuit Q over ESR...
BTW rumor has it that "SC cut" refers to HP works in Santa Clara CA where the SC cut was "discovered"...
Last edited:
I've always believe (maybe incorrectly) that basically the increase in noise is simply the equivalent increase in thermal noise of the crystals ESR...
Interesting question, does ESR also increase with increasing temperature? - one would expect it could / would, and where does this leave Q?
Last edited:
I should clarify my above post, the Leeson equation does not factor the temperature effects on the resonator element itself - sorry for any confusion, I was just pondering the effects of temperature on the series resistance and hence Q of the crystal (resonator)...
I don't recall ever seeing a mention of Crystal Q verse temperature...
On the subject of the Leeson equation, an excellent introduction can be found here:-
YouTube
I don't recall ever seeing a mention of Crystal Q verse temperature...
On the subject of the Leeson equation, an excellent introduction can be found here:-
YouTube
Last edited:
I have one of those
< https://ecsxtal.com/store/pdf/ECOC-2522.pdf >
available from Digikey. Not top notch, but OK for a SDR that must
stay on frequency. At the very least, it shows that there are 100 MHz SC cuts.
And for just € 100 anew in onesies.
I once claimed that SC was better than AT based on the commercial oscs
I knew the data for comparison, but got a harsh rebuttal from the owner of
the time nut list. He should know, he was one of the Santa Clara gang.
So I don't dare to lean that far out now. There stays the fact that SC
can take 3 times the dissipation, and a higher series resistance for the
same Q allows much deeper emitter degeneration in a Driscoll, for example.
That's good for the 1/f of the sustaining amplifier which is even better
for the close in noise because of the Leeson effect.
And the influence of the resistance of the tuning varicaps is smaller also.
You cannot do without them in a professional OCXO because just long
time stability or low phase noise is not enough. You must be be synchronous.
cheers, Gerhard
< https://ecsxtal.com/store/pdf/ECOC-2522.pdf >
available from Digikey. Not top notch, but OK for a SDR that must
stay on frequency. At the very least, it shows that there are 100 MHz SC cuts.
And for just € 100 anew in onesies.
I once claimed that SC was better than AT based on the commercial oscs
I knew the data for comparison, but got a harsh rebuttal from the owner of
the time nut list. He should know, he was one of the Santa Clara gang.
So I don't dare to lean that far out now. There stays the fact that SC
can take 3 times the dissipation, and a higher series resistance for the
same Q allows much deeper emitter degeneration in a Driscoll, for example.
That's good for the 1/f of the sustaining amplifier which is even better
for the close in noise because of the Leeson effect.
And the influence of the resistance of the tuning varicaps is smaller also.
You cannot do without them in a professional OCXO because just long
time stability or low phase noise is not enough. You must be be synchronous.
cheers, Gerhard
Last edited:
In an earlier post I alluded to areas where Matthys adaptation of the Healey/Driscoll XO circuit comprises Close-in phase noise - the LF feedback (Emitter degeneration) path is in fact via the Emitter inductor to Ground - which in Matthys circuit is only the inductors "DC" series resistance (a few ohms at most at LF) ... The Healey/Driscoll circuit has correctly added degeneration via a resistor in series with this Emitter inductor.
HF gain is restored by the loading capacitors across the crystal - I dont believe that the Crystals ESR which is in series with the Motional capacitance has any significant impact on Emitter degeneration - a fact supported by simulations I've worked on... but I'm opened to be corrected if I'm in error...
Oddly, Matthys in his book page 236 states:-
"The Purpose of the L2 (Emitter Inductor) in the circuit is not understood, but the circuit will not oscillate if L2 is Equal to or less than this resonance value, The circuit also will not oscillate if a resistor is substituted for inductor L2"
Well I understand the function of L2 is to provide a DC path for the transistor at LF and a much higher impedance at the resonant frequency (hence it cannot be simply replaced with a resistor)... this LF path should really be degenerated as in the original Healey/Driscoll Patent + the HF gain restored...
Last edited:
Again - I cannot be certain, but I'd be cautious in presuming that the SC cut crystal itself is operating at 100MHz. Whats typical is a resonate multiplier circuit in the collector load of a Colpits type XO circuit, so the SC cut Crystal could be say 33.333MHz with a x3 collector multiplier...
A quick search says SC cuts are now available from 0.5 - 200MHz so... maybe
The beauty of the Driscoll is that it is a current conveyor, with the upper transistor
degenerated by high collector impedance of the lower transistor, which is degenerated
by the current injection from the crystal. Even with a crystal Z of just 50 Ohms, the
transistors Re of maybe 2 Ohms is dwarfed, with the crystal dictating the game,
working into a near short circuit.
The Driscoll is a series resonance oscillator, and the tuning is made by a series C.
Capacitance in par to the crystal does nothing good and must be avoided. Even
C0 (static capacitance) must be tuned out at 100 MHz. That is the reason for
the ~uH inductor in par to the crystal that par-resonates with the ~2 pF C0 at 100 MHz.
They call that C0-compensation and it maximizes off-resonance neg. feedback.
With a large C you would short-circuit the series resonance.
That must not be a short at dc from emitter to GND or you get the full broadside of 1/f
noise from the transistor and that may be upconverted.
Remember that from the bottom transistor's world view, one could think that it
operates as a emitter follower. The collector is at low impedance from the Zin of the
upper transistor, base is the controlling input signal and the emitter circuit looks like
a high impedance follower load.
We all know what capacitively loaded followers like to do: oscillate at a GHz.
No wonder.
And don't get impressed by the fF capacitance and mH inductance of the crystal model.
It is still a series resonance at fres with 0 Ohms + the resistance for the finite Q.
The crystals Rser goes up with the square of the overtone, That's the reason
for those good 5 MHz overtone crystals. Of course, the L/C ratio still must fit
to reach the Q.
cheers, Gerhard
degenerated by high collector impedance of the lower transistor, which is degenerated
by the current injection from the crystal. Even with a crystal Z of just 50 Ohms, the
transistors Re of maybe 2 Ohms is dwarfed, with the crystal dictating the game,
working into a near short circuit.
The Driscoll is a series resonance oscillator, and the tuning is made by a series C.
Capacitance in par to the crystal does nothing good and must be avoided. Even
C0 (static capacitance) must be tuned out at 100 MHz. That is the reason for
the ~uH inductor in par to the crystal that par-resonates with the ~2 pF C0 at 100 MHz.
They call that C0-compensation and it maximizes off-resonance neg. feedback.
With a large C you would short-circuit the series resonance.
That must not be a short at dc from emitter to GND or you get the full broadside of 1/f
noise from the transistor and that may be upconverted.
Remember that from the bottom transistor's world view, one could think that it
operates as a emitter follower. The collector is at low impedance from the Zin of the
upper transistor, base is the controlling input signal and the emitter circuit looks like
a high impedance follower load.
We all know what capacitively loaded followers like to do: oscillate at a GHz.
No wonder.
And don't get impressed by the fF capacitance and mH inductance of the crystal model.
It is still a series resonance at fres with 0 Ohms + the resistance for the finite Q.
The crystals Rser goes up with the square of the overtone, That's the reason
for those good 5 MHz overtone crystals. Of course, the L/C ratio still must fit
to reach the Q.
cheers, Gerhard
Last edited:
Gerhard,
Thank you for taking the time to reply, I agree that Parallel C with the crystal is not a good thing except to provide antiresonace of the Co (Shunt capacitance) of the crystal - this is achieved with inductor 20, and C12, C22 & C24 in the original Patent...
These parallel capacitors also restore the HF gain otherwise degenerated by the Emitter series inductor / resistor combination...
I still maintain that the main transistor degeneration path is via the DC current path formed by the inductor and series resistor on the Transistors Emitter rather then the Crystals ESR (not the inductor in parallel with the crystal forming the Co antiresonace circuit)... again "My" simulations support this - but I make this claim cautiously as these simulations have not been peer reviewed in anyway...
Edit:-
Thinking about it in the simulations I also have a capacitor in series with the Crystals as part of the Co antiresonace circuit (C24 in the original Patent).... so this is in series with the Crystals ESR...
ASAP, I'll go back to the simulations and try to double confirm and report back the results
Thank you for taking the time to reply, I agree that Parallel C with the crystal is not a good thing except to provide antiresonace of the Co (Shunt capacitance) of the crystal - this is achieved with inductor 20, and C12, C22 & C24 in the original Patent...
These parallel capacitors also restore the HF gain otherwise degenerated by the Emitter series inductor / resistor combination...
I still maintain that the main transistor degeneration path is via the DC current path formed by the inductor and series resistor on the Transistors Emitter rather then the Crystals ESR (not the inductor in parallel with the crystal forming the Co antiresonace circuit)... again "My" simulations support this - but I make this claim cautiously as these simulations have not been peer reviewed in anyway...
Edit:-
Thinking about it in the simulations I also have a capacitor in series with the Crystals as part of the Co antiresonace circuit (C24 in the original Patent).... so this is in series with the Crystals ESR...
ASAP, I'll go back to the simulations and try to double confirm and report back the results
Last edited:
The point is that the degeneration is most important near DC to kill 1/f noise.
At RF, some emitter resistance is more important to linearize the amplifier
so what is left over from the 1/f cannot be upconverted. (and noise around harmonics)
Ideally, the amplifier should provide no gain, except at resonance, so please
as much negative feedback as possible everywhere else, and no ohmic
load resistor that could conspire with gm.
There is nothing worth amplifying but the carrier.
BTW I have written 2 simulation artices for DUBUS quite a long time ago:
< http://www.hoffmann-hochfrequenz.de/downloads/Hoffmann_VHF_Quarzoszillatoren_Teil1.pdf >
and
< http://www.hoffmann-hochfrequenz.de/downloads/Hoffmann_VHF_Quarzoszillatoren_Teil2.pdf >
It is more geared towards the Butler.
At RF, some emitter resistance is more important to linearize the amplifier
so what is left over from the 1/f cannot be upconverted. (and noise around harmonics)
Ideally, the amplifier should provide no gain, except at resonance, so please
as much negative feedback as possible everywhere else, and no ohmic
load resistor that could conspire with gm.
There is nothing worth amplifying but the carrier.
BTW I have written 2 simulation artices for DUBUS quite a long time ago:
< http://www.hoffmann-hochfrequenz.de/downloads/Hoffmann_VHF_Quarzoszillatoren_Teil1.pdf >
and
< http://www.hoffmann-hochfrequenz.de/downloads/Hoffmann_VHF_Quarzoszillatoren_Teil2.pdf >
It is more geared towards the Butler.
Last edited:
@JohnW: Very interesting discussion ... just out of curiosity - which values for 1 Hz, 10 Hz and 100 Hz carrier offset phase noise have you achieved with AT cuts (if you are ok with sharing this, of course)?
Cheers,
Jesper
P.S.: Might you also have a link to the Healey-Driscoll circuitry you are talking about? Although it admittedly is outside of my main field of experience it would nevertheless be interesting to see it, if possible ...
Cheers,
Jesper
P.S.: Might you also have a link to the Healey-Driscoll circuitry you are talking about? Although it admittedly is outside of my main field of experience it would nevertheless be interesting to see it, if possible ...
Last edited:
- Status
- Not open for further replies.