That's right, but the point is to actually see - if the noise increases, then how much (with no filter, with C, with RC), for Zener, LED, etc. I will publish some results in a separate thread.
Nice, but in another league. It is obvious that between 1ppm THD20 (the PGP amp) and 15ppm THD9 (your amp, by extrapolating, some 30ppm THD20) there is no audible difference; but strictly from a technology perspective, yours has 30dB less loop gain at 40KHz (20k second harmonic), while both having about the same phase margin. Extra 30dB, that's huge, and impossible to do with any 1 or 2 pole compensation schema.
However, I believe the PGP amp is the most uselessly over engineered amp ever built on this planet. It's sheering complexity is nothing but a "because I can" statement, and it's measured performances are nothing but numbers lacking any SQ relevance. I'll take any high output current 200W/4ohm amp, with 20ppm THD20, over the PGP.
Why are symmetrical slew limits the last thing one would want ??
Simply a CFA is better in this respect as much higher slew rates are possible.
Are you implying that simulations are unrealiable to verify whether a design can offer low distortion. Say a blameless amp simulates at - 100db THD and a other amp at -120db using the same device models, would that mean the blameless amp will in real life have lower THD despite the simulated results ??
With suitably asymmetrical slew limits, if HF oscillation or a big HF input signal occurs a DC offset will be produced that will trip the DC offset protection and disconnect the amplifier from the speaker, hopefully preserving your tweeters. Obviously both limits need to be high enough to pass good audio. See APAD6.
But not at all necessary. So it's not better.
No, I'm stating as a fact that simulation does not give accurate distortion results. It would be more accurate to say that simulation can show that a design cannot give low distortion, but not the reverse.
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I agree, and another problem is that many models do not include the tolerances of e.g. Vbe and Hfe, so Monte Carlo circuit analysis becomes useless.
Best regards
Jens
Doug,
Is this not why we add an input low pass filter?, to slew "limit" the amplifier so this doesn't occur. If this being the case wouldn't it make sense building a high slew rate amplifier even though it's not technically needed so we can slug the slew at the input and the amplifier has a walk in the park at hf?, not counting phase linearity at hf yet. Though as I read, you intentionally want to slew limit within the gain stage with an asymmetrical clip to dc protect speakers, namely tweeters?. From my understanding and on the ground observations from many others here we are often lucky if dc protection works as intended.
Colin
Is this not why we add an input low pass filter?, to slew "limit" the amplifier so this doesn't occur. If this being the case wouldn't it make sense building a high slew rate amplifier even though it's not technically needed so we can slug the slew at the input and the amplifier has a walk in the park at hf?, not counting phase linearity at hf yet. Though as I read, you intentionally want to slew limit within the gain stage with an asymmetrical clip to dc protect speakers, namely tweeters?. From my understanding and on the ground observations from many others here we are often lucky if dc protection works as intended.
Colin
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NO.
We add an input filter to limit the amount of RF garbage that appears at the amplifier input.
The race for slew rate originates from the concept of "slewing distortions" that are affecting an amplifier when the signal maximum rate of change is of the same order of magnitude with the large signal slew rate. For audio, 1V/uS for each output volt (40V/uS for a 100W/8ohm amplifier) is more that x10 this limit, so simply anything above is useless, whatever the Golden Ear Brigade will claim.
For audio amplifiers, CFAs (if they deserve this name, since... but I'd better stop here) with their gazillion of V/uS have absolutely no advantage over any correctly designed VFA.
In all truth, the vast majority of linear ICs today go to silicon straight from the designer computer screen. It's not the simulation per se that is lacking, but the huge amounts of money that corporates pour into defining and extracting (macro) models for their building blocks hierarchy.
I cringe and smile at the same time when I see here "use X (X=Cordell, Fairchild, etc...) models, they are so much better" and then recalling the 7 digit number that e.g. TSC is pouring in modeling and models for their design kits, every year. What people are using here as "simulation" belongs to the late 60's and early 70's, at best.
At this level, as Mr. Self already mentioned, simulation will tell mostly what will never work on the board, rather than revealing any absolute performance metric. Under these circumstances, the only decent way to use a Spice based simulator is to understand the role and side effects of certain devices and device parameters, that is, sort of variational analysis, rather than blindly trusting the absolute numbers.
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The simple Spice modelling that I do around here is also helpful because it allows me to learn more about how the circuit works. I'm no electronics engineer and by watching currents and voltages whilst I tweak parts of the circuit I can see what goings on. It's very handy indeed. (most of us know that distortion results are somewhat meaningless, a) because the models are suspect, b) because we don't model real world loads, c) because our ears tell us that the correlation with Spice is not 100%)
I noted that Doug (3rd edition) also uses Spice to initially explore the inner workings of different circuit blocks before taking them to the bench - it's a useful tool for doing that.
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More accurate to say that "many simulations do not produce accurate results".
I think you miss a major opportunity here. If a simulation does not yield accurate results then that is not a weakness of simulation, only of that simulation.
The opportunity is that any inaccuracy actually tells you that you have made a mistake, overlooked some factor that matters.
This can alert you to the importance of un-modelled components like trace inductance or capacitance, or other aspects that have been incorrectly assumed to be minor.
It is incredibly educational to see which overlooked factors really matter.
Then they can be measured and included.
The more accurate model is useful but the increased depth of comprehension is what I value more.
I have helped Toni (ASTX) develop or find better models for his Blameless amp.
It is now possible to pretty accurately predict not just distortion but also non-linear behaviour usually considered difficult, like clip/overload recovery and transient behaviour of the transformer at turn-on.
The Ovidiu/Stuart measurement results show what is possible in the area of distortion simulation.
It took effort but the distortion for that amp was well simulated even at the sub PPM performance level.
Best wishes
David
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See PGP for a built sub ppm amplifier employing fully balanced design techniques.
Blameless designs can be simmed that also show sub ppm, or near sub ppm performance as can fully balanced and CFA varieties. I have no doubt that with care in layout and construction, the non- blameless designs can also perform excellently - as the PGP showed.
I don't agree with your assertion that slew rates should be unsymmetrical since there are hundreds of fully balanced amp designs out there that have been manufactured in volume with no problems and they measure well. I rather suspect that the non-symmetrical,behavior of the blameless is a flaw and there is a neat theory to turn that into a design plus. Much in the same way most JFET input amplifiers need a servo, which is now positioned as a virtue while balanced bipolar amp can be DC coupled and does not end a servo.
Agreed, Your book is very factual, but I think you err a little too much on the 'there's only one way to design an amp'.
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PGP is not fully balanced, it is as single ended as it can be.
Whatever amount of care you'll put into the layout and construction, you are not going to get sub-ppm distortion in any standard Blameless, VFA, CFA, etc... You don't need a simulator to figure out this simple truth.
The "secret sauce" of the PGP is the 3rd order compensation, that provides the extra loop gain for linearizing. You can't get the same amount of loop gain from a 1st order (Miller) or 2nd order (standard two pole compensation, TMC - or output inclusive as, Mr. Self calls it, etc...), while maintaining the same phase margin.
The other point you need to consider is that your circuit is just an emitter-follower, not a 3-stage amplifier with global feedback and a dominant pole.
I don't want to discourage you, but your results will have very limited application to a full-scale power amplifier.
Effective DC protection is not hard to design. I have been using the same basic approach for 20 years in quantity production, on amplifiers ranging from 20 to 250W/8R, and I have yet to hear of an occasion of it not working when required.
Loudspeakers are expensive, and this is an area of design that should be treated very seriously.
This schematic is not a balanced input, but in the context of this discussion it is all push/pull complementary "balanced" IPS and VAS, plus the usual push/pull OPS.
Best wishes
David
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I want a book that explore all amplifier topology. What the strengthen and weakness. And let reader decide which one topology is best for their need. Because how it sound is very subjective.
I learn from this forum, and found many point of view how to design an amplifier, what most importance specification is.
1. THD profile is most importance
2. Lowest as posible THD value is most importance
3. Slew rate is most importance
4. IMD is most importance
And what minimum value of each specification should achieve?
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