So if I program York as 3 channels I2S stream, then standard Windows drivers will detect York as 5.1 sound card?
Another question, if I sometimes want to listen to a 2.1 stereo stream instead of 5.1, do I need to change the settings in Windows from 5.1 to stereo, or reprogram York? Will it be possible to switch from 5.1 to 2.1 under Windows without problems? Or does Windows not support the 2.1 configuration?
Now it will be seen as just 2/4/8 channel. To tell windows the exact configuration (3.1/5.1/7.1) a modification of USB descriptor is required. I have plan to do so but it is not there yet.
It depends on the software, sometimes it is possible to override "global" settings in windows inside the app. If you're up to do some experiments, I'll send you Nano board, I think it would fit into your DSP amplifier project. Please send me PM with address.
A new firmware is available:
v4.7 build 2434 (28 April 2025)
Bug fix: Mute signal in multichannel mode
v4.6 build 2424 (27 April 2025)
Bug fix: I2S input channel swap in slave mode
Please use latest config tool for update.
v4.7 build 2434 (28 April 2025)
Bug fix: Mute signal in multichannel mode
v4.6 build 2424 (27 April 2025)
Bug fix: I2S input channel swap in slave mode
Please use latest config tool for update.
In relation to York, just sugestion! 2.54 pins and I2S is not an good option in my opinion, thats an antenna + pickup antenna. And if possible an miniature board like esp32 or bluetooth module, something like this would be very good option for those who need things real modular in much smaller possible form = the better! That case users have choice to have miniature York and other to have miniature board + carier board whith size of current York, that way you have two options for selling and we have also two options for buying! In my case I not like the current size of the York and also not like those 2.54 pin headers. Just my sugestion for your further work on improving your York.
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There is a miniature version:
https://www.tindie.com/products/eclipsevl/york-nano-pic32mz-development-board/
It is still 2.54 but in smaller format. I was thinking of making this version with constellated holes, but it is too expensive for small batches.
https://www.tindie.com/products/eclipsevl/york-nano-pic32mz-development-board/
It is still 2.54 but in smaller format. I was thinking of making this version with constellated holes, but it is too expensive for small batches.
Yes but the issue is not related to paneling.
The constellated holes option triggers more expensive assembly option. And just because of that manufacturing cost for batch of 25 boards doubles (!)
The constellated holes option triggers more expensive assembly option. And just because of that manufacturing cost for batch of 25 boards doubles (!)
You should use v-cut on the side that do not have holes, and make square pads with oval holes so that you cut the rest of panel yourself, that way I think it not cost twice?
If I understood you correctly, you propose to cut the boards after production to get kind of constellated holes.
In that case there will be issue with metallization - the existing metallization in the holes can be damaged and there will be no metallization on the edge of the board. This is the whole point of constellated holes option.
It can be cut and the inside of the hole can remain some Cu, but it is not recommended because it can be broken. I will try it at some point
Hi eclipsevl
Just a quick question, could an isolated version of York with a relocking board be used in the 2ch in, 4ch out mode?
More specifically how would the 2ch i2s input be delt with in this hardware configuration
Just a quick question, could an isolated version of York with a relocking board be used in the 2ch in, 4ch out mode?
More specifically how would the 2ch i2s input be delt with in this hardware configuration
Hello,
The reclock board is designed just for 2ch I2S/PCM output, and the ISO version I2S input port can only work as master (because of the on-directional isolators).
So I would say it is not the right choice. It would be better to use non-isolated version and add isolation and clocks on another board to meet requirements of your project.
The ISO board may still work however with some restrictions:
1. Both In and Out I2S ports must be masters
2. Sampling frequency of input and output must be set to same value (both 48kHz or 192kHz, for example. 44.1 and 48 would not work)
These are SiTime, SiT8208
New firmware release, 4.8
Improvements: I2S input in slave mode now doesn't affect sampling frequency setting of I2S output.
It affect modes "2ch I2S input" and "Nch I2S output + 2ch I2S Input". Master clock grid would be defined by output sampling frequency selection.
New mode added: 8 channel TDM input
Improvements: I2S input in slave mode now doesn't affect sampling frequency setting of I2S output.
It affect modes "2ch I2S input" and "Nch I2S output + 2ch I2S Input". Master clock grid would be defined by output sampling frequency selection.
New mode added: 8 channel TDM input
An update on the project:
apparently, with carefully written assembly code for FIR calculation, it is possible to implement x8 interpolation on PIC32MZ MCU.
It is already done by the guy who started PIC32MZ project (Aleksey, mentioned in the first post), and together we are trying to make it faster. There is an interesting discussion going on in another forum 🙂
Yesterday my FIR implementation was faster, today it is the opposite. But it is already fast enough for x8 stereo interpolation at 44.1/48kHz.
The coefficients we use implement SM5842 filter.
This might be useful for the cases when PCM DACs directly interface York, for example.
apparently, with carefully written assembly code for FIR calculation, it is possible to implement x8 interpolation on PIC32MZ MCU.
It is already done by the guy who started PIC32MZ project (Aleksey, mentioned in the first post), and together we are trying to make it faster. There is an interesting discussion going on in another forum 🙂
Yesterday my FIR implementation was faster, today it is the opposite. But it is already fast enough for x8 stereo interpolation at 44.1/48kHz.
The coefficients we use implement SM5842 filter.
This might be useful for the cases when PCM DACs directly interface York, for example.
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The ISO version is out of stock, I am expecting new batch in 2 weeks.
Pico USB-C/USB-B and Nano versions are available.
Pico USB-C/USB-B and Nano versions are available.
A quick update on the DSP features.
I have made a first ASRC implementation for York. Of course York can just use external clock but in some cases ASRC still may be required. For example, if one needs to input I2S stream into PC and do not worry with matching the sample rate in Windows settings - ASRC would handle that. Another case is simultaneous input and output of audio from/to PC. Or to stream 44.1k/48k content from PC if only one masterclock frequency is available.
This is first implementation which is a bit simplified from the target, thus has a bit higher THD.
Especially at high frequencies.
Simulation of current ASRC implementation at 15kHz 0dB input tone:
Blue is the input at 352.4kHz, orange - oversampled to 384kHz.
There are many harmonics up to ~-113dB level.
Simulation of target model:
The THD is much lower, harmonics are below -148dB.
And the test with real hardware with oversampling from 88.2kHz to 192kHz.
The 30kHz harmonic level matches well at around -115dB. 15 kHz is close to the worst case for this implementation. In comparison, this is how 1.5kHz looks like:
With that it may be possible to add S/PDIF input as well. Not sure at this moment but I may try in the future.
I have made a first ASRC implementation for York. Of course York can just use external clock but in some cases ASRC still may be required. For example, if one needs to input I2S stream into PC and do not worry with matching the sample rate in Windows settings - ASRC would handle that. Another case is simultaneous input and output of audio from/to PC. Or to stream 44.1k/48k content from PC if only one masterclock frequency is available.
This is first implementation which is a bit simplified from the target, thus has a bit higher THD.
Especially at high frequencies.
Simulation of current ASRC implementation at 15kHz 0dB input tone:
Blue is the input at 352.4kHz, orange - oversampled to 384kHz.
There are many harmonics up to ~-113dB level.
Simulation of target model:
The THD is much lower, harmonics are below -148dB.
And the test with real hardware with oversampling from 88.2kHz to 192kHz.
The 30kHz harmonic level matches well at around -115dB. 15 kHz is close to the worst case for this implementation. In comparison, this is how 1.5kHz looks like:
With that it may be possible to add S/PDIF input as well. Not sure at this moment but I may try in the future.