I hate to drag you into continued posts when you'd like to be done with it, but my interpretation of your words leaves huge doubt in mind. I have to check.
So by 1.1Meg in parallel with input and upstream, do you mean this?
I'll be surprised if you do. but this is what I hear when you say it.
So by 1.1Meg in parallel with input and upstream, do you mean this?
I'll be surprised if you do. but this is what I hear when you say it.
No, the goal is to present a 1Meg resistive input to the probe -for low frequencies at least: at higher frequencies, the capacitance dominates-.
This is how to do it, but Ifind the VLF resistance disturbing low. The bootstrap might not work as intended in the sim. AFAIk, the physical circuit behaves as intended.
This is how to do it, but Ifind the VLF resistance disturbing low. The bootstrap might not work as intended in the sim. AFAIk, the physical circuit behaves as intended.