Hi Dellama,
My layout is universal - suitable for the tube, jfet and bjt versions - see >HERE<
Next post (#26) shows the jfet version, adapted for the lower rails.
Also, there is a beautiful single-pcb layout, made by PCB Magician - Alex_mm - >HERE<
Also, Terry (Still4given) may have some extra boards as soon as he receives them from the workshop - pls check with him if interested.
If you have questions or some special requirements - let me know.
Cheers,
Valery
My layout is universal - suitable for the tube, jfet and bjt versions - see >HERE<
Next post (#26) shows the jfet version, adapted for the lower rails.
Also, there is a beautiful single-pcb layout, made by PCB Magician - Alex_mm - >HERE<
Also, Terry (Still4given) may have some extra boards as soon as he receives them from the workshop - pls check with him if interested.
If you have questions or some special requirements - let me know.
Cheers,
Valery
Hi Valery,
My OPS boards came today and I wanted to populate a pair. Just to be clear, I should only install the 220p caps on the 2SK1058 side of the board?
Thanks, Terry
My OPS boards came today and I wanted to populate a pair. Just to be clear, I should only install the 220p caps on the 2SK1058 side of the board?
Thanks, Terry
Thanks, I was hoping this project was suitable for retrofitting an old broken amp I have in the basement. A 200W/8R amp works out to about 56V rails so I'll be at about 300W/8R with 70V. The schematic for my amp box says it's a 70V regulated supply with a -105dB noise floor so it should make a pretty good foundation for this design if I can get a suitable part up front. The amp is over 10 kilo so supply should be sufficiently stiff and heatsinking adequate. If not, i can probably add caps I'd like at least sub 20ppm distortion throughout the bandwidth with a minimum phase margin of 65%. Will this get me there without a tube?
Hi Terry, you're absolutely right - only one side, the one with 2SK1058. Between the gate and the drain.
Cheers,
Valery
This is generally possible, even with the higher phase margin. I just have to check the compensation values - will come back soon 😉
OK, did some fine-tuning for the option with 2SK117 jFETs at the input - optimal performance is reached at around 75 degrees of phase margin. I will publish appropriate values tomorrow.
Hi Valery,
I have the OPS complete and playing, however, I looked back through the thread and don't see wht to set the bias at. Can you please tell me what you have yours set at?
Thanks, Terry
I have the OPS complete and playing, however, I looked back through the thread and don't see wht to set the bias at. Can you please tell me what you have yours set at?
Thanks, Terry
Ah! Right, good point 🙂
The best performance is observed at 80-100mA per pair. Having source resistors 0.1R each and measuring at two of them in series (0.2R), this equals to 16-20mV.
My test heatsink is a bit smallish, so I keep it at the lower end (16mV -> 80mA).
Note, how smoothly the bias adjusts and how stable it sits once it's set to certain value - lateral FETs rock 😎
Here is a link to a Texas Instruments application note (AN-1645) that has an excellent treatment of bias issues for several types of power MOSFETs. The article focuses on how to marry their LM4702 driver chip to MOSFET output stages, but as part of the discussion it documents the bias current needed for each device to operate in its negative temperature coefficient region, which improves thermal stability without requiring thermal tracking in the output stage.
http://www.ti.com/lit/an/snaa045a/snaa045a.pdf
For the 2SK1058/2SJ162 pair, good thermal stability was achieved at a bias current of about 115 mA (see page 12). But as Valery points out, higher bias currents will require sufficient heat sinking.
I hope this is helpful.
Ray
Thanks Ray, very good paper. Makes our life easier - somebody has already tested lots of things 😉
That was my take as well when I started working on a hybrid design. That paper will also make it easier to adapt a design to different output devices, knowing what bias conditions are optimal for each.
Hi Ray,
Thanks for the link. A good read.
Hi Valery,
I have the OPS hooked up to a pair of OS's Spooky Leach IPS. Approximate output of the IPS is 4.7mA. Running at +-57V rails the lowest the bias will go is 27mV across a pair of emitters. I imagine with the TubSuMo IPS we will need more adjustment. Should I change to 100R trimmer?
Thanks, Terry
Thanks for the link. A good read.
Hi Valery,
I have the OPS hooked up to a pair of OS's Spooky Leach IPS. Approximate output of the IPS is 4.7mA. Running at +-57V rails the lowest the bias will go is 27mV across a pair of emitters. I imagine with the TubSuMo IPS we will need more adjustment. Should I change to 100R trimmer?
Thanks, Terry
Hi Terry,
Interesting. In fact, the lower the R is, the lower the bias is. That means, you've got 27mV at zero R.
My IPS runs with about twice as much current at the output (specially pupped-up for better driving the FETs directly), however I get 12mV at zero R. And 50R is enough in my case, as a matter of fact...
Are you sure you've got 27mV at zero R pot?
Interesting. In fact, the lower the R is, the lower the bias is. That means, you've got 27mV at zero R.
My IPS runs with about twice as much current at the output (specially pupped-up for better driving the FETs directly), however I get 12mV at zero R. And 50R is enough in my case, as a matter of fact...
Are you sure you've got 27mV at zero R pot?
Hi Valery,
Yes, I just checked and both pots are at zero R. Fully warmed up, I get 27.5mv across a pair on one channel and 31mv on the other. I'm sure the outputs can handle that bias, but will it go up with the other IPS? Odd that yours isn't high as well. Did you use Renesas Laterals?
Yes, I just checked and both pots are at zero R. Fully warmed up, I get 27.5mv across a pair on one channel and 31mv on the other. I'm sure the outputs can handle that bias, but will it go up with the other IPS? Odd that yours isn't high as well. Did you use Renesas Laterals?
Yes, I've got Renesas as well...
What I would recommend then - use 1N5711 schottky diode instead of 1N4148 there (same as you use in IPS) and try the higher value pot. Schottky has got the lower voltage drop, so your lowest bias will go down, and then you compensate it with appropriate R.
What I would recommend then - use 1N5711 schottky diode instead of 1N4148 there (same as you use in IPS) and try the higher value pot. Schottky has got the lower voltage drop, so your lowest bias will go down, and then you compensate it with appropriate R.
Yes, right. However, the best fit in your case will be BAT42 or BAT43.
For a test, you can just put a wire jumper over the diode and use a 200 ohm pot (start with zero R). Or put a 100R resistor instead of the diode.
Can you please measure the voltage drop between PD+ and ND- at OPS input after you set, say, 100mA (20mV) across a pair of outputs.
For a test, you can just put a wire jumper over the diode and use a 200 ohm pot (start with zero R). Or put a 100R resistor instead of the diode.
Can you please measure the voltage drop between PD+ and ND- at OPS input after you set, say, 100mA (20mV) across a pair of outputs.
Doh, sorry. I decided to do another test and hooking up an ammeter along with measuring across the emitters revealed I had a problem. With the emitters measuring 22mv I only have 39mA current per rail. That is when I noticed I used 1R emitters instead of 0R1. I don't have any so will try some 0R22 for now and order some 0R1.
Blessings, Terry
Blessings, Terry
To be honest, I doubted something like this at some point 😀
Then I thought - maibe this is due to some difference in FET parameters...
OK, cool
