I speak fluent Norwegian so I can tell you what was written
Translated; "Enjoy yourselves"
That's a bit odd coming from you, you yourself use "same sex" FET's, N-chn conduct equally well in both directions etc. Even Flatlabs use N-chn only in his M2 buffer stage.
-- EDIT --
If you are thinking about the gate polarity, I can always throw in the Linear Systems LSJ74-SOT-23 3L - there's your P-chn replacement
it is not odd from me...... I'm using N polarity JFets in my constructions , which are not having same type of "core" as UGS;
it's well known what UGS is , and you must have N and P polarity of JFets if you want to build one
whatever else you change , making changes in construction due to scarcity of P channel JFets , well - it isn't UGS anymore
so , adequate P and N channel JFets , and world is your oyster ...... as I said - everything around the core itself is piece of cake
Yes I understand that the original UGS use complimentary pairs and that can be arranged by pairing either a Toshiba or On Semiconductor N-chn vith
Linear Systems P-chn replacement for the 2SJ74-BL / 2SJ109-BL.
I believe that the core would still be intact even if only N-chn was implemented, but hey... its just an opinion and maybe I am wrong
First of all: No I don't understand it more than ZM or Pass.
Second: I have no intention of altering the circuit or schematic in such a way that it is no longer true to the original in regards to function.
Third. The reason I am speculating in using N-chn only is the availability of really good N-chn JFets and BJTs which I covered a few posts back. P-chn FETs are in decline and its just a matter of time before only N-chn is available. The only company that supply a P-chn of value is Linear Systems and in the form of the LSJ74.
I have already contacted them regarding the LSJ74-B and LSJ74-C in the SOT-23 3L package
Please note that I am planing for a single FET version and a paralleled FET version. No matter, both will have the SOT-23 FET socket, that opens the possibility for testing multiple FETs on the same card (FET-rolling). If -IF - the N-chn only VS Complimentary call for a different PCB, then there will be 3 different PCB's besides the additional Buffer stage which is featured in the UGS MUSES edition.
Rest assure, before anything is officially released, simulation and prototyping will happen. And yes, I listen to advices. Meaning, that if a N-chn only UGS is not recommended, then that affectively mean this version will not be developed - simple as that
- EDIT -
After all, these conversations and more, IS the reason I am doing this project in the public domain, and, if there are others who wish to have their own version, which I know there are.
Oneminde
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Anyone who is reading. My goal, besides building a preamplifier for myself is to future proof this version, as good as I can. Meaning that it should be able to build one 10 years from now. That might seem like a long time, but remember, the original UGS is from 2004/5 unless one count the original N.Pass UGS which featured the SuSy architecture, then we are talking 1999 or thereabout. So, my efforts is not to upset anyone but rather do as much as possible in a positive spirit while maintaining the originality as much as possible.
there is no word about upsetting ....... I'm simply stating that UGS architecture is calling for N-P Jfets in its core , nothing else
trying to help you , also stating that's sole critical thing , everything else is doable with current nowadays parts and you even have broad choice for that
buffers in front and after UGS are different issue - make them as you wish , but when speaking about UGS cell itself , that's it
you can make damn good car without Ferrari engine (using some other one) , but if you want to call it Ferrari - you must use Ferrari engine
trying to help you , also stating that's sole critical thing , everything else is doable with current nowadays parts and you even have broad choice for that
buffers in front and after UGS are different issue - make them as you wish , but when speaking about UGS cell itself , that's it
you can make damn good car without Ferrari engine (using some other one) , but if you want to call it Ferrari - you must use Ferrari engine
True
- That could also mean we should use 100% original parts, and that is a bit of a challenge these days. It is possible to source the original FETs, but due to them only being available through collectors and no one really knows how long they are available, its something I cannot recommend. So, here we are. Its kinda sad actually. I'd love to use the original.*******
Since we "can't", then that forces use to go in a different but similar direction. So, I'll make it very simple. The primary goal from now is to design it using complimentary N- and P-chn JFETs. This include the monolithic and parallel version.
Please note that I will not act as a source for the Linear Systems LSJ74 SOT-23 P-chn JFet since it is available through L.S or any of their vendors. Also, because I have not made a firm decision just yet which of the two N-chn JFET I want to use (see #58 and 59, page 6 in this thread), the Idss grade of both the N- and P-chn must match, that is why both the B and C grade for the LSJ74 is of interest.
Regarding Idss grade, you can look at it like this:
LSJ74-B should match very nicely to Toshiba 2SK209-BL - Idss: 6-12mA (for both)
LSJ74-C should match very nicely to On Semiconductor 2SK3557-6-TB-E - Idss; 10-20mA forth both. If you spend some time with the transistor test chart published in the JFet Companion and post #58 you will see that the On Semiconductor 2SK3557 and Linear Systems LSK170 performs similar.
Linear Systems LSK170-B/C is available as SOT-23 package. Meaning, we can run with Linear Systems for both the N- and P-chn. Both packages has a Pd of 400mW.
Using Linear Systems only will increase the cost, but perhaps that is not an issue in the grand scheme of things.
The BJTs will be replaced, that is non negotiable
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JFETs
And here I was thinking no one besides me will like the design or build a UGS MUSES in 2019. The stakes have risen, there is more of a general responsibility now
- All in all, this mean that we will pair the LSK170-B and LSJ74-B.
- Each buffer call for 2 of each per side: (2 pcs LSK170 and 2 pcs LSJ74) and since we have a left and right channel, we need 4 pcs LSK170 and LSJ74. So if you want to build all 3 buffer stages, you will need 12 pcs LSK170 and 12 pcs LSJ74.
- Depending on how closely matched they are will will impact the overall performance slightly, there will therefore be some minor differences in performance between each build. The closer their Idss is matched, the better it will be and there is no such thing as too close. Wile one might get away with up to 10% (which is quite common for dual packages), since we will use monolithic, matching to 1% or less should be achievable. But this depend on how close Linear System's yield is and how many you buy.
- This is the heart and soul of the UGS Buffer.
A side note:
I'm not sure how much power is dissipated through each BJT, but I know each side consume roughly 600mW or 0.6VA at full voltage swing and gain. If we don't take into consideration circuit losses, the absolute max dissipation would be 600mW / 8 BJT = 75mW - This calculation is probably off but its the best I can do for now.
If 75mW is the maximum for each BJT, then that puts the Toshiba Toshiba 2SC3324-L/2SA1312-L in a safe zone since it has a Pd of 150mW, that effectively mean that the BJT will only work at 50% of its maximum.
And here I was thinking no one besides me will like the design or build a UGS MUSES in 2019. The stakes have risen, there is more of a general responsibility now
- All in all, this mean that we will pair the LSK170-B and LSJ74-B.
- Each buffer call for 2 of each per side: (2 pcs LSK170 and 2 pcs LSJ74) and since we have a left and right channel, we need 4 pcs LSK170 and LSJ74. So if you want to build all 3 buffer stages, you will need 12 pcs LSK170 and 12 pcs LSJ74.
- Depending on how closely matched they are will will impact the overall performance slightly, there will therefore be some minor differences in performance between each build. The closer their Idss is matched, the better it will be and there is no such thing as too close. Wile one might get away with up to 10% (which is quite common for dual packages), since we will use monolithic, matching to 1% or less should be achievable. But this depend on how close Linear System's yield is and how many you buy.
- This is the heart and soul of the UGS Buffer.
A side note:
I'm not sure how much power is dissipated through each BJT, but I know each side consume roughly 600mW or 0.6VA at full voltage swing and gain. If we don't take into consideration circuit losses, the absolute max dissipation would be 600mW / 8 BJT = 75mW - This calculation is probably off but its the best I can do for now.
If 75mW is the maximum for each BJT, then that puts the Toshiba Toshiba 2SC3324-L/2SA1312-L in a safe zone since it has a Pd of 150mW, that effectively mean that the BJT will only work at 50% of its maximum.
I stand corrected. To clarify why I call it a buffer, that comes from a few months back when I thought the two stages used in the UGS MUSES was divided into a voltage and current buffer - but that is not the case since the UGS module is fully capable of doing both the voltage and current gain - as far as I know, the BJT's architecture is Current Mirror which is; "We know that in a transistor operating in its active mode, collector current is equal to base current multiplied by the ratio β (or the [hfe] of the device). So a device with higher [hfe] value will yield a higher gain.
Flat did mention this himself: "UGS 3: Current Mirrors"
Source: Current Mirror BJTs | Bipolar Junction Transistors | Electronics Textbook
So... lets dump the wording Buffer and simply call the UGS the gain stage as we should. Thanks for pointing it out ZM
The maximum [hfe] of the ZTX450/550 is 300 and since Flat did not mention if he did transductance matching, besides looking at the gain he mentioned.
Gain:
1) On Semiconductor BC850/860-C (SMD equivalent to BC550/560)
- [hfe] 420-800 - General voltage is 45-50V - NF: typ 1.2dB - Pd: 310mW - Input Capacitance: typ 9pF - Output Capacitance: typ 3.5pF.
2) Toshiba 2SC3324-L/2SA1312-L
- [hfe] 350-700 - General voltage is 120V - NF: typ 0.2(0.5)dB - Pd: 150mW - Output Capacitance; typ 3pF.
The question is which [hfe] we should aim for ? - this is currently open for inputs.
Flat did mention this himself: "UGS 3: Current Mirrors"
Source: Current Mirror BJTs | Bipolar Junction Transistors | Electronics Textbook
So... lets dump the wording Buffer and simply call the UGS the gain stage as we should. Thanks for pointing it out ZM
The maximum [hfe] of the ZTX450/550 is 300 and since Flat did not mention if he did transductance matching, besides looking at the gain he mentioned.
Gain:
1) On Semiconductor BC850/860-C (SMD equivalent to BC550/560)
- [hfe] 420-800 - General voltage is 45-50V - NF: typ 1.2dB - Pd: 310mW - Input Capacitance: typ 9pF - Output Capacitance: typ 3.5pF.
2) Toshiba 2SC3324-L/2SA1312-L
- [hfe] 350-700 - General voltage is 120V - NF: typ 0.2(0.5)dB
- Pd: 150mW - Output Capacitance; typ 3pF.The question is which [hfe] we should aim for ? - this is currently open for inputs.
We will simplify a little, I hope that purists will not mind. So to schematize, the UGS is composed of two stages: differential pairs in input (in complementary symmetrical) - Jets - and stage "level down" - Mosfets in common source assembly.
We will first take an interest in the open-loop gain of the assembly (Gbo) by removing the counter-reaction resistances (Rin = 0 and Rfb = infinite).
The first stage has an intrinsic gain G1:
G1=-gmf*Rdf/(gmf*Rsf+1)
gmf: transconductance of a JFet (~ 25mS @ 3.5mA for 2SJ / 2SK)
Rdf: drain resistance of JFets (1K5)
Rsf: JFets source resistors (47R)
G1 is the differential gain, ie the ratio (Vd + - Vd -) / (Vin + - Vin-) where the Vd are the AC voltages on the drain resistors of the JFets. The sign "-" in the gain reflects the phase inversion of the diff amp.
The second stage, we are lucky. Its gain is given by the same formula:
gmm: transconductance of a BJT (~ 40mS @ 7mA)G2=-gmm*Rdm/(gmm*Rsm+1)
Rdf: drain resistance (here it is Rout that plays this role, 1K)
Rsf: source resistors (470R)
So the open loop gain of the SKU is simply the product of the two-stage gains:
Gbo = G1 * G2 = gmf * * gmm Rdf Rdm * / ((* gmf Rsf + 1) * (gmm * Rsm + 1))
With the values used, it gives us a Gbo of about 34.8, or 30.8dB
Now, the feedback resistors Rin and Rfb are returned to the circuit.
We will call "B" the ratio Rin / Rfb.
All the good electronic works give you the gain of a counter-reactioned montage like:
G = Gbo / (1 + B * Gbo)
With our values of Rin = 15K and Rfb = 56K, we get a G gain of 3.37, or 10.5dB
This is the differential gain, ie (Vout + - Vout -) / (Vin + - Vin-)
The "asymmetric" gain, the output voltage on a branch divided by the input voltage on a branch (Ga = Vout + / Vin +) is half the differential gain, or 6dB less, 4.5dB or 1.68. That's what you'll get if you measure like me on one output and one input.
In practice, we actually have a little less. Indeed, the transconducances of JFets and mosfets are slightly different and difficult to estimate in the real case. I was able to measure for example around 4dB (in asymmetric) with my UGS for these values of resistances.
So to size your gain, rely on an open loop gain between 30 and 35, set a Rin between 15K and 22K, and calculate Rfb based on that to get the desired gain. And readjust as needed.
Well, it is outrageusemet simplified (it does not take count of the effect of Rcm for example), but it is not far from the truth. If there are volunteers to make the exact calculations, they are welcome
Sincerely
François
JFets
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noise is irrelevant there , it's not MC stage
so , to repeat - JFets are cruciall , everything else - cascode BJTs (Q1,2, 3, 4) are piece of cake ( counting on chosen/max Iq in core of - say - 5mA per side - calculate dissipation , then you can use smd parts , taking care of heatsinking and dissipation not greater than 50% of declared
same calculus for inner ring of current mirror bjts - Q5,6,7,8 - same Iq as previous , figure out CE voltages for dissipation calculus ; Hfe is not critical - any small BJT is having high enough Hfe that you can stop even thinking about
outer ring of CM bjts - Q9,10,11,12 - Iq is doubled comparing to core , EC voltage is rail voltage
again - Hfe is not critical - any small BJT is having high enough Hfe that you can stop even thinking about
just in case - fact is that presented UGS is DIY iteration of Pass UGS - for my knowledge Pa never made CM iteration - it was always JFets in core , cascoded with bjts , mosfets in outer ring (modulated with JFet drain resistances)
not saying which one is better - with moderate CLG , I couldn't hear too much difference between these ......... though , I wasn't interested investing too much time in listening differentiations .....
so , to repeat - JFets are cruciall , everything else - cascode BJTs (Q1,2, 3, 4) are piece of cake ( counting on chosen/max Iq in core of - say - 5mA per side - calculate dissipation , then you can use smd parts , taking care of heatsinking and dissipation not greater than 50% of declared
same calculus for inner ring of current mirror bjts - Q5,6,7,8 - same Iq as previous , figure out CE voltages for dissipation calculus ; Hfe is not critical - any small BJT is having high enough Hfe that you can stop even thinking about
outer ring of CM bjts - Q9,10,11,12 - Iq is doubled comparing to core , EC voltage is rail voltage
again - Hfe is not critical - any small BJT is having high enough Hfe that you can stop even thinking about
just in case - fact is that presented UGS is DIY iteration of Pass UGS - for my knowledge Pa never made CM iteration - it was always JFets in core , cascoded with bjts , mosfets in outer ring (modulated with JFet drain resistances)
not saying which one is better - with moderate CLG , I couldn't hear too much difference between these ......... though , I wasn't interested investing too much time in listening differentiations .....
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