Ach So... "The magic mountain"... good writer! This Beatnik's period was said to be fantastic especially in USA and Germany...
Asked you because my first name is close but has an other origin as coming from an anargyr saint of Anatolia...
It's not off topic as today it is the All Saints' Day !
Come back to the subject : does it make sense to put a good phase XO like the Laptech if the phase is a little "wasted" by the TTL ? Or placing the XO at the reverse or farer of the TTLs could be a good enough trade off ?
Why not directly a unique lowest possible sampling rate for the Library we have : e.g red book or upsampled by the soft reader like Foobar ? I.E. : 2.xxx Mhz for the TDA1541 or the greatest possible if Library is upsampled ?
Of course it means a ceratin coherence in the Data Library : a unique upsampling (or not) fhz ? And of course makes only sense if the design needs it to solve the limitations of the trade off...
Saw some use FGPAs to produce clock bit: Is the phase measurement worst ? Does it need also a XO before ?
Our different needs (different sources needs) ask a lot of efforts to Andrea...
Asked you because my first name is close but has an other origin as coming from an anargyr saint of Anatolia...
It's not off topic as today it is the All Saints' Day !
Come back to the subject : does it make sense to put a good phase XO like the Laptech if the phase is a little "wasted" by the TTL ? Or placing the XO at the reverse or farer of the TTLs could be a good enough trade off ?
Why not directly a unique lowest possible sampling rate for the Library we have : e.g red book or upsampled by the soft reader like Foobar ? I.E. : 2.xxx Mhz for the TDA1541 or the greatest possible if Library is upsampled ?
Of course it means a ceratin coherence in the Data Library : a unique upsampling (or not) fhz ? And of course makes only sense if the design needs it to solve the limitations of the trade off...
Saw some use FGPAs to produce clock bit: Is the phase measurement worst ? Does it need also a XO before ?
Our different needs (different sources needs) ask a lot of efforts to Andrea...
WHat is this torture tool ?
I saw a lot of people talked of what was done in the last Chord little Dac about good clock design but certainly not for all the diyers Tools box ?
The first idea of Andrea was to design a good clock with a very good supply for him TDA 1541 project. But as he is a nice guy and a gentleman I believe he opened the project for more needs.
What i don't understand because my few knowledge is what are the SQ limit of those trade offs in relation to the sota expensive Laptech Crystal choice ?
In my simple mind the simplier the better but I know also digitals RF boards are very complicated... so... naive questions could came from me !
And any option where we do have to let the micro chip's legs solderd by a supplier adds to the cost...
I saw a lot of people talked of what was done in the last Chord little Dac about good clock design but certainly not for all the diyers Tools box ?
The first idea of Andrea was to design a good clock with a very good supply for him TDA 1541 project. But as he is a nice guy and a gentleman I believe he opened the project for more needs.
What i don't understand because my few knowledge is what are the SQ limit of those trade offs in relation to the sota expensive Laptech Crystal choice ?
In my simple mind the simplier the better but I know also digitals RF boards are very complicated... so... naive questions could came from me !
And any option where we do have to let the micro chip's legs solderd by a supplier adds to the cost...
ECL is a very fast logic family but its notuseful if you can't make use if its signaling. Most of the chips (DAC's line receivers etc.) that support audio use 3.3V logic and ar CMOS. ECL is actually a negative voltage current steered logic. For CMOS designs it has evolved into LVDS, which is similar. However if the chip doesn't use the logic it brings nothing useful to the table.
The 74AC logic's phase noise contribution is way below what these oscillators are capable of. Its not an issue.
The 74AC logic's phase noise contribution is way below what these oscillators are capable of. Its not an issue.
Demian, if I remember correctly you tried potato logic, is this worth using wrt jitter performance or noise compared to AC?
Thanks. I thought this might be the case due to the differential nature.
I believe they (Potato) have internal bypassing? If this is the case did you
experience any interaction with external bypass caps.
I hope you are not implying they might be going away due to lack of demand
It's very different...
Basically the 74 logic behaves like a comparator. It has no memory. The comparator threshold is simply VCC/2 plus self noise.
If you input a clock with 1V/ns risetime (classic 3ns risetime for 3.3V), and the comparator threshold moves 1mV, then you get 1mV/1V*1ns = 1ps jitter.
Since self noise is much lower than that, most of the noise will come from VCC.
If you do not do anyting stupid like feed your clock buffer from the same LDO and decoupling caps as some big DSP, even if you use a 20c LDO, you'll never get 1mV noise on the output... most likely 10-100x lower, which results in really low jitter levels.
And what happens in the previous clock edge is unrelated to what happens in the next clock edge, it has no memory of past events.
HOWEVER a clock is different, it has memory, think of it like a wheel that is turning, powered by a motor, and the angle is the phase. If you lower the power supply voltage during one second and then bring it back to the previous value, then it is going to turn a little slower during one second, and even when restoring the voltage, it will return to its previous speed (frequency) but the angle (phase) will never catch up. It will always be a little late compared to what its phase would have been if the power supply had not changed.
A clock has a dF/dV spec which is the frequency variation depending on VCC variation. The phase (which is what we are interested in, as in phase noise) is the integration of frequency. Therefore, the phase varies with the integral of VCC noise and self-noise. This is why noise is so important in clocks, self-noise, VCC noise, vibration, etc. The absolute phase of the output "remembers" all the past history of those.
A clock buffer just copies, but an oscillator creates a clock, and it is much easier to copy than create. So you can stick a 10c buffer with a 10c LDO and a few caps on your $100 clock and not degrade it.
Actually if you use a DAC which supports a crystal (like ES9018) it will have an input able to handle low voltage levels. So I guess it would be possible to capacitive couple input an ECL clock into an ES9018, although I have not tried. However the huge advantage of ECL/LVDS is that they are balanced. This would throw away this advantage and just result in a low level single ended signal. This would probably be much more sensitive to noise than good old CMOS levels. In other words, who cares.
FPGAs have PLLs and DCMs which will multiply an incoming clock by a factor of your choice. You can also divide. It is very practical. If using LVDS/ECL you can get decent phase noise, because the chips are optimized for that, because noone would use single-ended CMOS for a jitter sensitive clock on a board full of fat DSPs and FPGAs. However using plain CMOS, the jitter will be rather high, since all ground and power supply noise inside the chip will affect it. I would not do that.
What's wrong with sticking the oscillator 2cm away from the DAC ? More complicated solutions aren't always better...
Hi Peufeu,
thanks for the inputs.
My understanding with all those input pcbs for I2S DAC is there is always one device too far from the XO.
If not the DAC this is the Xmos of the USB or of the SD card which need to be fed by the same XO. So Xo near the dac chip and far from the input is maybe bad but the opposite should a same bad thing... (I mean without Fifo or repeater + buffer).
And with all those too big Uf.L cables (4" the sortest I found) the length is maybe too long and add some jitter as well (in theory, don't know myself as i have no scope nore any clue how to work with it) !
Well it's a trade off as we have pain to do a all in one compact DAC with a collaborative work on DIYA (too much complicate and also too different needs about the input stage. We sucess instead of a good collaborative like with this thread or other like the Distinction-TDA 1541.
In theory the board Andrea is developping is maid to be stacked above the distinction-TDA 1541 printed by RyanJ fellow at 100 ex.
But here also many different needs. E.g. : iF i success to have the Ian's PCM board for simultaning mode and a Wave I/O from Lorien : how to feed them all from the Andrea board : will need 3 outputs for MCLK : one for the Ian PCB and two for the Wave I/O... impossible, so I will use those boards for another project than the Distinction and keep the Andrea XO board for a non I2S simultaned mode for the Distinction-1541 with e.g. a more simple Amareno whic can be fed on a simplier way by an external clock like the Andrea's one. At least i hope so.... hum have to correct my needs in the waiting list for two crystals : 22 & 24 Mhz... And here also no Amareno maid with isolator or uf.l connectors for its inputs like its outputs !
But I encourage Andrea to do the less trade off in relation to the final quality for him own needs
Peufeu, sorry off topic may you advise me please about a good and simple output stage for a AD1862 DAC in PM ?
regards
Eldam
thanks for the inputs.
My understanding with all those input pcbs for I2S DAC is there is always one device too far from the XO.
If not the DAC this is the Xmos of the USB or of the SD card which need to be fed by the same XO. So Xo near the dac chip and far from the input is maybe bad but the opposite should a same bad thing... (I mean without Fifo or repeater + buffer).
And with all those too big Uf.L cables (4" the sortest I found) the length is maybe too long and add some jitter as well (in theory, don't know myself as i have no scope nore any clue how to work with it) !
Well it's a trade off as we have pain to do a all in one compact DAC with a collaborative work on DIYA (too much complicate and also too different needs about the input stage. We sucess instead of a good collaborative like with this thread or other like the Distinction-TDA 1541.
In theory the board Andrea is developping is maid to be stacked above the distinction-TDA 1541 printed by RyanJ fellow at 100 ex.
But here also many different needs. E.g. : iF i success to have the Ian's PCM board for simultaning mode and a Wave I/O from Lorien : how to feed them all from the Andrea board : will need 3 outputs for MCLK : one for the Ian PCB and two for the Wave I/O... impossible, so I will use those boards for another project than the Distinction and keep the Andrea XO board for a non I2S simultaned mode for the Distinction-1541 with e.g. a more simple Amareno whic can be fed on a simplier way by an external clock like the Andrea's one. At least i hope so.... hum have to correct my needs in the waiting list for two crystals : 22 & 24 Mhz... And here also no Amareno maid with isolator or uf.l connectors for its inputs like its outputs !
But I encourage Andrea to do the less trade off in relation to the final quality for him own needs
Peufeu, sorry off topic may you advise me please about a good and simple output stage for a AD1862 DAC in PM ?
regards
Eldam
Last edited:
Thanks for your expalantion. I have to admit my understanding of clocks and crystals was subject to a serious degree of under-development
To check what I think to have understood: For low jitter, the quality of the PS of the clock-generator is crucial. Voltage-stability and low-noise are top priority. Correct?
Hi Essigt,
i don't want to answer for Peufeu, but think I can reply as I already asked the same as you :
For a low jitter you need firstly a XO graded as low jitter with a good phase noise.
then the goal is after on the layout to avoid those qualities to be wasted :
- good layout : complex : impedance matching, EMS problem, shielving, separation of the active trace, time propagation, oscillations... not limited list as many things are involved and don't have a clue of most of them.
- good compacity : not too much, too long trace and connection grow the jitter but too compact give self polution : radiation on the traces on the others, ps transformer too close, etc...
So yes Voltage stability but also its harmonic noise structure has to be seen... like one of the very long list of top priority: avoiding oscilations after a good low and stable voltage by a bad decoupling, etc.
At least that's my understanding. Others will add corrections if false. try to look at Marce threads here or elswhere as he gives very often a lot of usefull didactic documents (links, pdf) to educate us... I understand just 10% of the reading but have the feeling to sleep less fool than the day before
regards
i don't want to answer for Peufeu, but think I can reply as I already asked the same as you :
For a low jitter you need firstly a XO graded as low jitter with a good phase noise.
then the goal is after on the layout to avoid those qualities to be wasted :
- good layout : complex : impedance matching, EMS problem, shielving, separation of the active trace, time propagation, oscillations... not limited list as many things are involved and don't have a clue of most of them.
- good compacity : not too much, too long trace and connection grow the jitter but too compact give self polution : radiation on the traces on the others, ps transformer too close, etc...
So yes Voltage stability but also its harmonic noise structure has to be seen... like one of the very long list of top priority: avoiding oscilations after a good low and stable voltage by a bad decoupling, etc.
At least that's my understanding. Others will add corrections if false. try to look at Marce threads here or elswhere as he gives very often a lot of usefull didactic documents (links, pdf) to educate us
... I understand just 10% of the reading but have the feeling to sleep less fool than the day beforeregards
In the close to the carrier region, with a slope of 9 dB/octave, the noise of an oscillator is due mainly to the flicker noise of the active device used and to the power supply noise.
I would also add the imperfections of the crystal surfaces, that's the reason I recommended an heavy polished crystal.
In the subsonic region the noise of an oscillator could be affected also by moving air.
A good tutorial about the phase noise modeling (Leeson's equation)
http://www.ieee.li/pdf/essay/phase_noise_basics.pdf
I would also add the imperfections of the crystal surfaces, that's the reason I recommended an heavy polished crystal.
In the subsonic region the noise of an oscillator could be affected also by moving air.
A good tutorial about the phase noise modeling (Leeson's equation)
http://www.ieee.li/pdf/essay/phase_noise_basics.pdf
Also vibration can be significant. Crystals are sensitive even to gravity. Its possible to measure the change in frequency from turning an oscillator on its side. Good vibration isolation is really important.
However below some threshold these effects will not translate through a DAC. They are just too small. If its below 24 bits it really has no way to show through to the output.
However below some threshold these effects will not translate through a DAC. They are just too small. If its below 24 bits it really has no way to show through to the output.
Jitter only really matters on D/A and A/D conversion. On digital signals it matters only if there is enough of it to cause bit errors, which is really uncommon. XO near DAC chip is optimal...
Also I don't specially like UFL : they're annoying to use, fragile, and the shielding effectiveness is bad at audio frequencies (thin shield). It is much better than the usual wires flying everywhere, but if you really want some coax, get plumbing pipe, or the bare cable from ebay and solder your favourite connectors.
Nothing in stock, sorry.
Last edited:
- Status
- Not open for further replies.