You got a squeaky clean line with the dummy but I can see some modulation on the first picture. Use two wire mode and JFET instead of R6 to see if it gets any better or its just the logic gate noise propagating on the rail.
How can we wired the JFET: d+g one leg and s the other leg or etc...? wich JFET: sk117, sk170, etc?
How can we wired the JFET: d+g one leg and s the other leg or etc...? wich JFET: sk117, sk170, etc?
replace r6 with 117gr
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Idss is measured with G+S and D as input.How can we wired the JFET: d+g one leg and s the other leg or etc...? wich JFET: sk117, sk170, etc?
This operates in a circuit as well and gives a good CCS.
One would not normally connect D+G and use S as output.
Except that jFETs are reputedly virtually symetrical. One can swap D & S and get virtually the same performance, particularly with those intended for RF duty.
But this would be D+G and S as input, not output.
Have I to increase R1 2 ohms?
2.2 even
After changing R1 for 2R (I don't have 2R2) and the SK117GR for R6, now Vout 5.158VDC current 316mA (0.631V across 2R). Some pics:
1st left connected the FF & isolator both powered R-D
2nd BiB only powering Amanero
3h connected only FF without isolator powered R-D
1st left connected the FF & isolator both powered R-D
2nd BiB only powering Amanero
3h connected only FF without isolator powered R-D
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BTW, you can see best when using the ground spring instead of the crocodile wire on the probe. Probe's GND wire is an antenna.
An externally hosted image should be here but it was not working when we last tested it.
I arrived the same conclusion Flip Flop generates noise as listened.
Maybe needs an RCRC filter?
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