From the device datasheet:
"All unused inputs of the device must be held at VCC or GND to ensure proper device operation."
See the note after section 6.3.
Ray
You don't seem to have populated the LP filters either on the PCB picture. Hazard has had good results with his Llundahl transformers but I had noise with my silk TVCs until I installed LP filters before it - will be interesting to see if your transformers are successful.
As you have no isolation they'll both (Amanero ground and FlipFlop Ground) need to be connected to your ground arrangement.
I think you'll need to have some ground isolation to get the best out of this.
Ray
The LED will stay lit until you sent PCM data (not recommended). The voltage at pin 8 will latch to 3V when you send DSD data, even after a power down. You don't have a problem to worry about with the LED.
Ray
Ah, lol, ok. I admit I was worrying to have inverted the power for a moment... So...
Btw, anyone using oscillator board on JLSounds card?
Inviato dal mio D5803 utilizzando Tapatalk
Btw, anyone using oscillator board on JLSounds card?
Inviato dal mio D5803 utilizzando Tapatalk
If the power connections were reversed the LED wouldn't turn on at all - it's a diode.
Ray
Yep, I meant... Reversed the main 5V... 😛
Inviato dal mio D5803 utilizzando Tapatalk
Do they have to be connected either ALL to VCC or ALL to GND? The note is unclear, talking about connecting to the nearest one.
I have connected them all to GND apart from pin 13 to VCC. With no power supply to the flip flop I get sound on the left channel alone. I guess it is due to capacitative coupling. Supplying the flip flop with 5V, now I get the usual hum plus a whistling sound on the left channel.
Thanks for your continued input.
I read it as they all need to be one or the other, not a mixture. On the flipflop PCB they are all connected to Vcc and that works for me.
Ray
JLSounds DSD Signal Loss Idea
I designed and ordered a PCB that substitutes a 6Mhz square wave signal for the DSD signal when the DSD signal has stopped for about 30us. This PCB will plug directly onto the two rows of 10pin connectors of the JLSounds board. This PCB will also include 1:9 buffer ICs (PCS2P2309NZ) to have 9 CMOS outputs driving each RC filter.
There is an 11.2896MHz/12.288MHz signal from pin 20 of the JLSounds board whenever there is power to pin 12. This signal is present even when there is no USB signal/5V or external power to pin 1 of the JLSound board. I will derive a 5.645MHz/6.144MHz signal from a dual 4-bit binary counter (74LV393). I will use the LDSD signal to reset the 2nd half of the counter. If this counter reaches 196 clock counts without a LDSD reset, then logic gates will change the output streams from L&R DSD to the “0 analog” bit steam going to the DSD RC filters. The resumption of DSD bits will immediately switch the output back to the DSD data streams. This should eliminate the need for a mechanical relay.
If this works I will post schematic and pictures. I will also report if this doesn’t work as hoped.
I designed and ordered a PCB that substitutes a 6Mhz square wave signal for the DSD signal when the DSD signal has stopped for about 30us. This PCB will plug directly onto the two rows of 10pin connectors of the JLSounds board. This PCB will also include 1:9 buffer ICs (PCS2P2309NZ) to have 9 CMOS outputs driving each RC filter.
There is an 11.2896MHz/12.288MHz signal from pin 20 of the JLSounds board whenever there is power to pin 12. This signal is present even when there is no USB signal/5V or external power to pin 1 of the JLSound board. I will derive a 5.645MHz/6.144MHz signal from a dual 4-bit binary counter (74LV393). I will use the LDSD signal to reset the 2nd half of the counter. If this counter reaches 196 clock counts without a LDSD reset, then logic gates will change the output streams from L&R DSD to the “0 analog” bit steam going to the DSD RC filters. The resumption of DSD bits will immediately switch the output back to the DSD data streams. This should eliminate the need for a mechanical relay.
If this works I will post schematic and pictures. I will also report if this doesn’t work as hoped.
Thanks for posting Carlsor, it sounds very interesting. I look forward to seeing how it works out.
Cheers
Ray
Cheers
Ray
JLSounds DSD DC Offset Removal Idea
One more idea:
It is my understanding that the RC filter/relay boards for the JLSounds function as a 40KHz low pass filter, but do not remove the 1.65V DC offset which remains after filtering.
While looking for digital buffers to provide a stronger signal though the RC filter I found a write-up by Analog Devices Company for using their 350MHz AD8057 op amp with a 3Hz high pass input filter to function as a high speed digital clock buffer.
I designed and ordered a simple PCB with a 1uf/47K 3.4Hz input high pass filter and a dual opamp AD8058 with a gain of +2 to drive a 40KHz low pass RC filter. The JLSounds DSD bit streams would have the 1.65V DC offset removed by the input HPF and then be driven through the RC filter by the more powerful op amps.
I will post how this works.
One more idea:
It is my understanding that the RC filter/relay boards for the JLSounds function as a 40KHz low pass filter, but do not remove the 1.65V DC offset which remains after filtering.
While looking for digital buffers to provide a stronger signal though the RC filter I found a write-up by Analog Devices Company for using their 350MHz AD8057 op amp with a 3Hz high pass input filter to function as a high speed digital clock buffer.
I designed and ordered a simple PCB with a 1uf/47K 3.4Hz input high pass filter and a dual opamp AD8058 with a gain of +2 to drive a 40KHz low pass RC filter. The JLSounds DSD bit streams would have the 1.65V DC offset removed by the input HPF and then be driven through the RC filter by the more powerful op amps.
I will post how this works.
Yes, simple first order. You can set the LP filter at different frequency should you choose.
For the single-ended board that is true and you need to use a cap. For the Balanced board the flipflop outputs differential signals and I measure negligible DC across those outputs.
Ray
@carlsor:
Hi .. I hope it's ok that I make a comment on this ...
To my knowledge one of the less than optimal characteristics of DSD is that it's quite sensitive to jitter in order to achieve a "higher" (yet not high) ENOB. Although I find your choice of buffer interesting due to the many GND pins (potentially low ground bounce?) I reckon that a potentially +/- 250 ps pin-to-pin skew will reduce ENOB (and maybe influence the sound?) quite some. If I remember correctly depending on the type of DSD converter (FYI I read about an ADC not a DAC) even one ps could effect the ENOB "some" (can't remember the exact figures - some years back that I read about this).
Personally I've been searching for a multiple FF with many GND pins and low FF-to-FF skew as well as a precise timing of clk pulse-to-pulse so as to get a low ground bounce and precise pin-to-pin timing. I may only have found this:
SN74LVC32374A
... but not exactly simple to layout if having a limited No of PCB layers.
If you'd like to use a buffer I can say that Herbert Rutgers for an audio clock oscillator has achieved a phase noise value of - 132 dB for a 10 Hz offset from carrier using a 74HC04 inverter. From reading in the TWTMC thread this seems to be not many dBs from the very best there is.
http://www.diyaudio.com/forums/digi...se-jitter-crystal-oscillator.html#post4051205
Another (I would say knowledgeable) suggestion in this thread has been to use a 74HCU04 (due to only one buffer circuit per inverter).
Cheers,
Jesper M
Hi .. I hope it's ok that I make a comment on this ...
To my knowledge one of the less than optimal characteristics of DSD is that it's quite sensitive to jitter in order to achieve a "higher" (yet not high) ENOB. Although I find your choice of buffer interesting due to the many GND pins (potentially low ground bounce?) I reckon that a potentially +/- 250 ps pin-to-pin skew will reduce ENOB (and maybe influence the sound?) quite some. If I remember correctly depending on the type of DSD converter (FYI I read about an ADC not a DAC) even one ps could effect the ENOB "some" (can't remember the exact figures - some years back that I read about this).
Personally I've been searching for a multiple FF with many GND pins and low FF-to-FF skew as well as a precise timing of clk pulse-to-pulse so as to get a low ground bounce and precise pin-to-pin timing. I may only have found this:
SN74LVC32374A
... but not exactly simple to layout if having a limited No of PCB layers.
If you'd like to use a buffer I can say that Herbert Rutgers for an audio clock oscillator has achieved a phase noise value of - 132 dB for a 10 Hz offset from carrier using a 74HC04 inverter. From reading in the TWTMC thread this seems to be not many dBs from the very best there is.
http://www.diyaudio.com/forums/digi...se-jitter-crystal-oscillator.html#post4051205
Another (I would say knowledgeable) suggestion in this thread has been to use a 74HCU04 (due to only one buffer circuit per inverter).
Cheers,
Jesper M
I am a newcomer to digital circuits so I need all the helpful comments that I can get from more experienced DIYers.
The SN74LVC32374A is far too complicated for me to use. I'm sticking with SOIC IC's for now. First time for me regarding the term "ENOB" so I looked it up. I could only find ADC PWM references so I don't know how it applies to DAC DSD.
What I am focusing on is the integrity of the DSD square waves entering the RC filter - no overshoot or oscillation, symmetrical, minimum rounding of corners, etc. There are Potato Semi equivalents to all but one of the ICs I am using with all ICs in the DSD signal path potentially being 100% Potato Semi. They claim an improved CMOS technology with higher frequencies and no noise or overshoot. My concern is that the RC filter might distort a single logic gate output square wave so I will be testing multiple parallel CMOS or AD8058 outputs. I have a scope so this should be interesting.
The SN74LVC32374A is far too complicated for me to use. I'm sticking with SOIC IC's for now. First time for me regarding the term "ENOB" so I looked it up. I could only find ADC PWM references so I don't know how it applies to DAC DSD.
What I am focusing on is the integrity of the DSD square waves entering the RC filter - no overshoot or oscillation, symmetrical, minimum rounding of corners, etc. There are Potato Semi equivalents to all but one of the ICs I am using with all ICs in the DSD signal path potentially being 100% Potato Semi. They claim an improved CMOS technology with higher frequencies and no noise or overshoot. My concern is that the RC filter might distort a single logic gate output square wave so I will be testing multiple parallel CMOS or AD8058 outputs. I have a scope so this should be interesting.
@carlsor:
Hi carlsor ... my apology for using this acronym without further explanation - it's short for "effective number of bits" and is a way of translating the resolution of e.g. a 1-bit signal into a multibit signal. E.g. a 22 MHz 1-bit signal with a given SNR, THD etc. may correlate with a 16 bit resolution (or something else). IMHO it doesn't necessarily relate to sound quality (as normal DSD if I remember correctly has a very low ENOB but may sound quite well).
Ok - might the MAX44205 be of interest to you? 400 MHz GBW, very low distortion, fully differential (equal loading of CMOS outputs if differential) and the datasheet high output scope photos indicate almost no overshoot, ringing.
And then a comment on using multiple ICs in DSD ... I did some (hopefully correct) calculations on jitter vs. track length and even a fraction of a millimeter may mean timing differences in the ps range. Just FYI ;-)
Good luck with your endeavours (and looking forward to reading about them if you would like to share) ...
Cheers,
Jesper
Hi carlsor ... my apology for using this acronym without further explanation - it's short for "effective number of bits" and is a way of translating the resolution of e.g. a 1-bit signal into a multibit signal. E.g. a 22 MHz 1-bit signal with a given SNR, THD etc. may correlate with a 16 bit resolution (or something else). IMHO it doesn't necessarily relate to sound quality (as normal DSD if I remember correctly has a very low ENOB but may sound quite well).
Ok - might the MAX44205 be of interest to you? 400 MHz GBW, very low distortion, fully differential (equal loading of CMOS outputs if differential) and the datasheet high output scope photos indicate almost no overshoot, ringing.
And then a comment on using multiple ICs in DSD ... I did some (hopefully correct) calculations on jitter vs. track length and even a fraction of a millimeter may mean timing differences in the ps range. Just FYI ;-)
Good luck with your endeavours (and looking forward to reading about them if you would like to share) ...
Cheers,
Jesper
Any reason that the flip flop board wouldn't work with this:
XMOS 768kHz DXD DSD512(DSD1024) high-quality USB to I2S/DSD PCB - DIYINHK
?
XMOS 768kHz DXD DSD512(DSD1024) high-quality USB to I2S/DSD PCB - DIYINHK
?
