till said:
There must be some chips made for I2S->4 lines conversion. No need for an µc for this.
Yes, I THINK that the I2S clock is 2.82MHz in a non os configuration
???
Guido,
do you want to do that to cancel RF garbage on the output ?
I had that idea too, but there was not much response to my thread...
guido said:
Guido,
do you want to do that to cancel RF garbage on the output ?
I had that idea too, but there was not much response to my thread...
Re: Using Xor gates is better than the inverter
You could use a noninverting buffer in the other line.
Calimero said:
You could use a noninverting buffer in the other line.
Can someone explain me the problem with I2S and dataline inversion?
And the difference that a XOR would do, compared to an inverter
And the difference that a XOR would do, compared to an inverter
rfbrw,
you wrote
i admit i don´t really understand:
From AD1865 datasheet:
Data is transmitted to the AD1865 in a bit stream composed of 18-bit words with a serial, twos complement, MSB first format.
From TDA1541 datasheet:
The TDA1541 accepts input sample formats in time multiplexed mode or simultaneous mode with any bit length. The most significant bit (MSB) must always be first.
looks both are MSB first. Is the twos complement the point?
you wrote
i admit i don´t really understand:
From AD1865 datasheet:
Data is transmitted to the AD1865 in a bit stream composed of 18-bit words with a serial, twos complement, MSB first format.
From TDA1541 datasheet:
The TDA1541 accepts input sample formats in time multiplexed mode or simultaneous mode with any bit length. The most significant bit (MSB) must always be first.
looks both are MSB first. Is the twos complement the point?
Bricolo, as i understand the XOR is only because some fear the inverter in only one of the datalines needs some time to invert and such one the inverted dataline is a bit laid back relative to the noninverted. This should be easy corrected by using a phase splitter or an additional buffer in the noninverting dataline.
The main proble seems to be we loose one bit, as guido posted: http://www.diyaudio.com/forums/showthread.php?postid=340783#post340783
The inersion of data isn´t really the inverted dataword.
The inverted dataline tells only 15 bit words to the DAC what means our - signal is one bit less accurate tha the + signal.
I would ignore the problem with the time allignement of inverted and noninverted word as it will be about nothing. We should better think about the lost bit.
The main proble seems to be we loose one bit, as guido posted: http://www.diyaudio.com/forums/showthread.php?postid=340783#post340783
The inersion of data isn´t really the inverted dataword.
The inverted dataline tells only 15 bit words to the DAC what means our - signal is one bit less accurate tha the + signal.
I would ignore the problem with the time allignement of inverted and noninverted word as it will be about nothing. We should better think about the lost bit.
till said:
I think, yes.
2's complement is a way of coding digital information, that has a special feature: when you invert the MSB, you change the sign of the coded number
that's all I know. But I'm not sure if it's usefull here, since we invert all bits, and not only the MSB
I don´t know is only for the AD1865 the dataword twos complemet or for I2S also?
because http://www.diyaudio.com/forums/showthread.php?postid=340803#post340803
i inverstigate on timing:
TDA1541
shows the timing: word clock changes 1 serial clock before last bit is clocked into DAC.
AD1865
shows the word clock changes direct after last bit of the word is clocked into DAC. DAC want a falling edge, such WCLK would have to be inverted for Left channel LL.
but now:
I2S out of Philips CD PRO2
surprise surprise, this doesn´t look like the I2S the TDA1541 does like. For me it looks more like the ADs timing. Whats going on here?
And again: is format twos complement only for AD or also in I2S?
So we would need some twos complement inverter for correct inversion.
because http://www.diyaudio.com/forums/showthread.php?postid=340803#post340803
i inverstigate on timing:
TDA1541
An externally hosted image should be here but it was not working when we last tested it.
shows the timing: word clock changes 1 serial clock before last bit is clocked into DAC.
AD1865
An externally hosted image should be here but it was not working when we last tested it.
shows the word clock changes direct after last bit of the word is clocked into DAC. DAC want a falling edge, such WCLK would have to be inverted for Left channel LL.
but now:
I2S out of Philips CD PRO2
An externally hosted image should be here but it was not working when we last tested it.
surprise surprise, this doesn´t look like the I2S the TDA1541 does like. For me it looks more like the ADs timing. Whats going on here?
And again: is format twos complement only for AD or also in I2S?
So we would need some twos complement inverter for correct inversion.
In case I2S has also twos complemet would interfacing the AD look like this?
twos complement words looks like this, it´s obvios simple inversion gives not the inverted value but is always wrong with 1.
An externally hosted image should be here but it was not working when we last tested it.
twos complement words looks like this, it´s obvios simple inversion gives not the inverted value but is always wrong with 1.
Attachments
The datasheets cover all this but here goes.
There seem to be a number of distinct issues being rolled into one.
Offset binary and 2's complement are issues in their own right. They cover the number formats and what the bits actually mean.
MSB first is about the orientation of the data.
Justification is about the position of the data word as a whole. Using the output of the CS8412 as an example each L/R frame has 64 bits i.e. 32 bits per channel. Right justified 16bit data would occupy bits 1 to 16 with the MSB for MSB first data in the bit 1 position. Left justified 16bit data would occupy bits 17 to 32.
The I2S bus is right justified with a quirk. 16bit data would occupy bits 2 to 17. Things are can be somewhat different with mono and simultaneous input dacs.
ray.
There seem to be a number of distinct issues being rolled into one.
Offset binary and 2's complement are issues in their own right. They cover the number formats and what the bits actually mean.
MSB first is about the orientation of the data.
Justification is about the position of the data word as a whole. Using the output of the CS8412 as an example each L/R frame has 64 bits i.e. 32 bits per channel. Right justified 16bit data would occupy bits 1 to 16 with the MSB for MSB first data in the bit 1 position. Left justified 16bit data would occupy bits 17 to 32.
The I2S bus is right justified with a quirk. 16bit data would occupy bits 2 to 17. Things are can be somewhat different with mono and simultaneous input dacs.
ray.
Thanks.
some still confusing things:
The I2S from the CD PRO 2 manual doens´t show the "quirk" , it looks like simply bit 1 to 16 are dataword. The TDA1541 datasheet shows the quirk, 2 to 17 are one word. Both I2S , both Philips, connect or not?
The AD can´t be connected because it wants left justified (last 18 Bit clocked into Dac are writen into shift register...) but I2S is right?
So the only way for AD DAC is using a CS8412 or CS8414 and SPDIF?
some still confusing things:
The I2S from the CD PRO 2 manual doens´t show the "quirk" , it looks like simply bit 1 to 16 are dataword. The TDA1541 datasheet shows the quirk, 2 to 17 are one word. Both I2S , both Philips, connect or not?
The AD can´t be connected because it wants left justified (last 18 Bit clocked into Dac are writen into shift register...) but I2S is right?
So the only way for AD DAC is using a CS8412 or CS8414 and SPDIF?
till said:
See Fig3 in post number #50
The CD Pro2 supports a number of formats. It can be configured using the DSA command set. See the manual. Yes, I2S is right justified.
No. Added logic between the CD Pro2 and the AD1865 is another option.
ray.
- I must be stupid, but i can´t see why figure 3 has the 1 bit offset. Maybe because quality of the diagramm is that bad i can´t read the numbers or words in the bits. To me it looks like one 16 bit word into one WCLK frame.
I have "USER MANUAL PREMIUM 10501" and "VAU1254bis.pdf" the Datasheet. I find the DSA commands, and i find there is a command set DAC mode 70h but all infoormation about the possible DAC modes given is parameter = XX; XX= don´t care. It doesn´t help me the VAU1254 is able to send in other formats as long as i have no table with parameters for 70h and diagramm or description of possible modes. In the docs provided with the unit they are not.
I fear its behind my skills. Not at least because it seems very difficult to find all information necessary. If i would have the equipment to programm a fast enough DSP or so, it would be possible to solve inverting the datawords and serve them in right format and order in software.
I have "USER MANUAL PREMIUM 10501" and "VAU1254bis.pdf" the Datasheet. I find the DSA commands, and i find there is a command set DAC mode 70h but all infoormation about the possible DAC modes given is parameter = XX; XX= don´t care. It doesn´t help me the VAU1254 is able to send in other formats as long as i have no table with parameters for 70h and diagramm or description of possible modes. In the docs provided with the unit they are not.
I fear its behind my skills. Not at least because it seems very difficult to find all information necessary. If i would have the equipment to programm a fast enough DSP or so, it would be possible to solve inverting the datawords and serve them in right format and order in software.
till said:
Can't see how you can miss it. Unless you are looking for the wrong thing.
The MSB of each 16bit word, i.e bit 1, is positioned one serial clock cycle after the transition of WDCLK.
70h is the command value that tells the device what the following value is for. You need to follow the value 70h with the value for the mode you require.
The document "DSA Interface Bus Protocol & DSA Command Set Premium 10501" lists the values for all possible output formats on page 31.
Digital Audio is slow. Glacially slow. Any DSP, never mind a fast one, would be wasted. Inverting the data, adding the 1 and then reordering the data would barely make a dent in the smallest sizes of the latest FPGAs and CPLDs. A few 74 series TTL chips or a XC9536 CPLD would make short work of connecting the CDPro2 to the AD1865.
ray.
Thanks, your help is invalueable. I found it.
But to fast for PIC, even at 40MHz i fear. I hope for DSPics. A Software for processing the Bitstream has the advantage its very easy to change format for different DACs. It would be possible to build different DACs in one unit and simply software switch them for example. And in case you do not develop for mass production but only one unit, its much easyer to make your mistakes in software as its easy to correct them.
Mucho posts here, hard to keep up.
Till,
Your previous tda schematic had le/ws unconnected. Just look at any of the schematic on the net for tda1541 connections. Never saw anything else but i2s. Forget a PIC for this, you need logic. DSP is indeed overkill.
Dont know if it would be a problem, but the DAC in the D1 circuit is 0mA out for 'dig silence' data in. That is because the internal current source of the PCM63 is used (the output pin is connected to another pin of the DAC, check it out).
A tda1541 is -2mA at rest, so the there is current running when
there is no music. Again, i'm not an analogue expert, so don't know if it matters. But i guess pass did not use the internal PCM63 current source for nothing! (reports are that it is better not to use it, but then your output circuit must be capable of handling this).
Bricolo,
If you go from i2s to "4 line format" you should check the way the data is coded (for 1541). From memory, it is different than the i2s coding. If so, inversion by just inverting the dataline might not be possible (after you created the separate datalines)! Check the datasheet and the used coding formats and start drawing.
I2S clock is 2.82 MHz because wordlengths are 32 bit (16 bit used, 16 unused) as for SAA7210 or the 8412. samplefreq = 44kHz times 64 = 2,816 MHz. E.g. 7220 output is 16 bit wordlenghts. So 44kHz * 4 (oversampling) * 32 = 5.632 MHz.
Bernard,
2Fs was just an idea, did not really look into it. TDA1541 is 0 to -4mA out.
I'll have a look into not inverting the LSB. Did not bother before (nobody did in any design i saw on the net (including D1). I wonder if it matters (is audible).
Greetings,
Till,
Your previous tda schematic had le/ws unconnected. Just look at any of the schematic on the net for tda1541 connections. Never saw anything else but i2s. Forget a PIC for this, you need logic. DSP is indeed overkill.
Dont know if it would be a problem, but the DAC in the D1 circuit is 0mA out for 'dig silence' data in. That is because the internal current source of the PCM63 is used (the output pin is connected to another pin of the DAC, check it out).
A tda1541 is -2mA at rest, so the there is current running when
there is no music. Again, i'm not an analogue expert, so don't know if it matters. But i guess pass did not use the internal PCM63 current source for nothing! (reports are that it is better not to use it, but then your output circuit must be capable of handling this).
Bricolo,
If you go from i2s to "4 line format" you should check the way the data is coded (for 1541). From memory, it is different than the i2s coding. If so, inversion by just inverting the dataline might not be possible (after you created the separate datalines)! Check the datasheet and the used coding formats and start drawing.
I2S clock is 2.82 MHz because wordlengths are 32 bit (16 bit used, 16 unused) as for SAA7210 or the 8412. samplefreq = 44kHz times 64 = 2,816 MHz. E.g. 7220 output is 16 bit wordlenghts. So 44kHz * 4 (oversampling) * 32 = 5.632 MHz.
Bernard,
2Fs was just an idea, did not really look into it. TDA1541 is 0 to -4mA out.
I'll have a look into not inverting the LSB. Did not bother before (nobody did in any design i saw on the net (including D1). I wonder if it matters (is audible).
Greetings,
Hi guido,
I changed the connection in post #40, i hope this way its correct.
Indeed i can forget a normal PIC as it is to slow and thus not easy to program in an way the bitstream comes out isochron. A DSP is much more difficult to get running, so its not the solution also. Logic may be easy for someone from the days IBM build ATs with about 200 TTL 74xxx ICs on mainboard. But for one who does not know all the logic chips by name and funktion and is not used to hardware logic its a pain and nothing else. Software is much more easy to handle. I hope there will be a MC with DSP features or a ten times faster MC soon, so it would be easy to do all it in software and one IC.
For the inverting: If we invert the twos complement incorrect (inverter) we loose information for - side of balanced DAC. So waveform on + and - is not symmetric. In this situation i estimate 2 parallel DACs, one of them running the out signal in an inverter / the other in a identical buffer ( 2 diff. pairs) would be better balanced signal than one were the - side is generated digitally but with assymterical waveform by principle.
I hope you or someone else skilled in 74xyz stuff will find time for a elegant solution for inverting the word and add 1, for a correct inverted signal. I´ll try some tests with simple interconnects of DACs to the transport. And hope i´ll find something to make the format transfomation and inversion with some kind of programmable one chip solution on the long run.
The -2 mA issue: does this mean range is from -2 to +2 mA ?
I changed the connection in post #40, i hope this way its correct.
Indeed i can forget a normal PIC as it is to slow and thus not easy to program in an way the bitstream comes out isochron. A DSP is much more difficult to get running, so its not the solution also. Logic may be easy for someone from the days IBM build ATs with about 200 TTL 74xxx ICs on mainboard. But for one who does not know all the logic chips by name and funktion and is not used to hardware logic its a pain and nothing else. Software is much more easy to handle. I hope there will be a MC with DSP features or a ten times faster MC soon, so it would be easy to do all it in software and one IC.
For the inverting: If we invert the twos complement incorrect (inverter) we loose information for - side of balanced DAC. So waveform on + and - is not symmetric. In this situation i estimate 2 parallel DACs, one of them running the out signal in an inverter / the other in a identical buffer ( 2 diff. pairs) would be better balanced signal than one were the - side is generated digitally but with assymterical waveform by principle.
I hope you or someone else skilled in 74xyz stuff will find time for a elegant solution for inverting the word and add 1, for a correct inverted signal. I´ll try some tests with simple interconnects of DACs to the transport. And hope i´ll find something to make the format transfomation and inversion with some kind of programmable one chip solution on the long run.
The -2 mA issue: does this mean range is from -2 to +2 mA ?
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