Simultaneous output Frontend for TDA1541 (and or Universal Multibit DAC) using discrete logic - Collaborators wanted

Yes I can even find this IC in local store...

Yes, it is the Last of FIFO Tribe.

I didnt mean "repaeat" as opperation, but the bit lenght will be determined with asinchroneus 1/4 of input BCK, so the content of output bit cell will be "automaticaly" be the same lenght as output clock?

Yes. The bit length is determines by the clock. it has no "length" in itself.

With a FIFO we have n storage locations (e.g. 16 with 40105) and unlike a shift register, the first bit in immediately ripples through to the output. The next incoming bit moves down to just before that and so on.

In programming we use the "stack" as a similar structure, except the stack is LIFO (Last In First Out).

What will be on other 3 inputs beside DATA line?

I propose 3pcs 40105.

One is simply used as 16 Bit storage to allow the two channel Data to be split out and aligned with WCK, so after this FIFO we have Data L / Data R with MSB aligned with rising edge of WCK.

For many DAC's that's actually all that's needed, as long as as they accept 16 Bit LJ. If we have more than 16 Bit and need RJ, simply add either a 8 Bit Shift register or another FIFO for a 32 Bit FIFO and apply the right flow control. It also allows stopped clock that makes sense for CMOS logic based DAC's.

Let's call that part "Data Splitter". The FIFO Full and FIFO Empty signals also provide provide flow control. For example, when the 16 Bit FIFO is empty we close the clock gate on BCK for the BCK out of the Data Splitter

Now we still have 64 X BCK, but we separated out data L/R and we can invert MCB with a bit of additional logic. For this we also need to make a 1 BCK wide pulse aligned with WCK, which we can use as LE.

Now we make a second FIFO out of 2 pcs 40105 (in theory one could be made to work, but the added flow control logic is onerous, more so than just making the FIFO longer.

This FIFO has the following inputs (@ 64 X BCK):

LE (the 1BCK long pulse that matches the MSB)
DATA_L
DATA_R
CTRL (control signal to detect FIFO 1/2 full)

The output of the FIFO gets a BCK at 16 X that is continuous. It is created from the main BCK reclocked by MCK and divided down. Need figure out the best Logic, in terms of phase noise. ECL has a lower LF corner but higher flat band noise and is a PITA to integrate with CMOS.

So I guess a chain of 74AC(T)74 is most likely to create the lowest phase noise.

New data appears on the falling edge, so we need to use the inverted BCK for the Reclocking circuit.

BCK, LE, DATA_L & DATA R will be buffered and reclocked by 1.8V "popcorn logic" with just a series resistor as signal conditioning.

As serial data is latched into the TDA1541 input register on the falling edge of BCK and transferred to the output register on the rising edge of LE all we need to do is get the polarity of the clock on the little reclock IC's right.

For BCK & DATA_L/R we just use two unbuffered popcorn logic buffers to get a 1.8V clock (again with series resistor as signal conditioner). It's not actually really jitter sensitive, so no need to loose a lot of sleep.

So we have for now:

Data Splitter

74ACT74 # 0 (WCK Delay by 1BCK, BCK Reclock)
74HC40105 # 0 (Data Splitter)
74HC86 (MSB Inverter)
74HCXX (Clock gate, flow control)

BCK Divider

74ACT74 # 1 (BCK to BCK/4 divider)

Output FIFO

74HC40105 # 1 (Output FIFO)
74HC40105 # 2 (Output FIFO)


Popcorn logic for TDA1541 Signal Conditioning

NC7SZ175 (LE Reclock)
NC7SZ125 # 0 (DATA_L 1.8 Level shifter)
NC7SZ125 # 1 (DATA_R 1.8 Level shifter)
NC7SZ125 # 2 (BCK_O 1.8 Level shifter)


The Level converter IC's may very well use 74AUC1G instead. It's still at the idea stage.

Thor
 
Hello there,

Sorry to ask,

But why is a fifo needed if a masterclock is slaving the recloker shitregisters that are nearer to the DAC chip ?

The fifo is swapping the isolator, but anyway it will be recloked in both scenario so what makes it superior to a FGPA as all is recloked ?

Better timing of the Bck, Wlck and datas elative to each others ?
 
But why is a fifo needed if a masterclock is slaving the recloker shitregisters that are nearer to the DAC chip ?

No, what we do is to not use sh!(f)tregisters. We use FIFO instead.

If we want to do this with shiftregisters

The fifo is swapping the isolator, but anyway it will be recloked in both scenario so what makes it superior to a FGPA as all is recloked ?

????

Am not sure what all of this means.

We are talking about a circuit that accepts bog standard IIS input with theoretically up to 32 Bit per channel and hence a bit clock of 64FS that outputs then Simultaneous format with separate data lines per channel and a bit clock of 16FS.

It is all about conversion between formats.

Reclocking and signal conditioning I consider part of the TDA1541.

Depending on using IIS Mode or SIM mode the actual update (I am avoiding "conversion") of the output is timed by BCK (IIS) or LE (SIM). So only this clock is in need of "re-clocking".

The important parts of digital input signal conditioning for the TDA1541 (and ONLY THIS PART!) are to limit the voltage swing, where 1.8V should be fine, we avoid the input leaving linear operation doing that and to limit the slew rate, where according to Kirchoff the same slew rate achieved by low value resistor and extra capacitor or just a series resistor cause the same noise current into the substrate and coupling into the rest of the circuit.

So in my view, using slew rate controlled "popcorn" logic like 74AUC1G125 or 74AUC1G175 with around 2.7...3.3k series resistor is the sweet spot between effectiveness and circuit complexity.

Much more complex circuits do not really improve the outcome, fewer parts would need 1.8V versions of the FIFO which does not exist. A resistive divider of 8.2k + 4.7k may offer the same outcome as the extra buffer. These are details I will get into near the end.

Thor
 
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What will be on other 3 inputs beside DATA line?

I propose 3pcs 40105.
Sorry it was a misunderstanding
I mean inputs in FiFo IC
D0, D1, D2, D3 of each IC
We need just one input Dn per channel.
.
And for 2 channels, Simultaneous we need
2 x Fifo for 32bit Left ch datas, (first 1/2 of LE)
2 x FiFo for 32 bit Right ch data (second 1/2 of LE)
.
Data line consisting of serial cascade of 2 x FiFo for each channel.
Asynchronous operation,
input clock = I2S bit clock
Output clock = input clock divided by 4
(Take a look at read clock and D1)

FiFo asychronous.png

.
And we need 1/2 LE line to make 16bits "window"
negative for enabling output controlled by "memory 16 bits full", output clock is on
additionally with bursts to reset after memory is "empty"
...
I can draw the circuit for determining MSB and invert the MSB.
.
I found very useful TI PDF about FiFo basics
.
 

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Sorry it was a misunderstanding
I mean inputs in FiFo IC
D0, D1, D2, D3 of each IC
We need just one input Dn per channel.

I think carrying the LE too is neat.

And for 2 channels, Simultaneous we need
2 x Fifo for 32bit Left ch datas, (first 1/2 of LE)
2 x FiFo for 32 bit Right ch data (second 1/2 of LE)

Not for TDA1541. Only if you want to handle > 16 Bit. Which I do not.

I only need 1 16 bit FIFO for data splitting.

Did you look at my data/clock graph in the post I linked a few pages back?

Data line consisting of serial cascade of 2 x FiFo for each channel.

I plan on using 3 out of the 4 data to carry data left, data right, latch enable for the FIFO feeding into the TDA1541.

Asynchronous operation,
input clock = I2S bit clock
Output clock = input clock divided by 4
(Take a look at read clock and D1

Not sure I follow what you are trying to do.

And we need 1/2 LE line to make 16bits "window"

No, we use a 16 Bit FIFO, the FIFO full indicator also indicates this point.

negative for enabling output controlled by "memory 16 bits full", output clock is on
additionally with bursts to reset after memory is "empty"

I think you are overcomplicating things.

Have you looked at the data/clock diadram I posted?

I can draw the circuit for determining MSB and invert the MSB.

Inverting use ExOr. In my proposed design we delay WCK by 1 BCK. So WCK rising edge indicates MSB. We use a one shot flip flop that is reset by BCK.

I found very useful TI PDF about FiFo basics

Thank you, I understand how they work.

Thor
 
"Sorry it was a misunderstanding
I mean inputs in FiFo IC
D0, D1, D2, D3 of each IC
We need just one input Dn per channel."

I think carrying the LE too is neat.
Then 2 other FiFo input lines will be empty...
...

Probably it can be done just with 2 FIFO iCs
But it depends how long FIFO can sustains the data before Output clock is appeared and output Enable is ON, and data released?
If FIFO can store for 32+16 original BCK then 2 ICs are enough...
...

plan on using 3 out of the 4 data to carry data left, data right, latch enable for the FIFO feeding into the TDA1541.
No, we use a 16 Bit FIFO, the FIFO full indicator also indicates this point.
No the LE from "FIFO FULL output would not be in the same place as original LE. It Will be delayed for amount of time that all bits are filled in. So it will be "theoretically" in the place that should be but most probably it will have some fluctuations...
Anyway it should be compared to the 1/2 of original LE period it should be there...

Inverting use ExOr. In my proposed design we delay WCK by 1 BCK. So WCK rising edge indicates MSB. We use a one shot flip flop that is reset by BCK.
It already present on the sch I posted few posts before, (use F-F instead of shift register)

Thank you, I understand how they work.
OK Yes, but this is th public forum and maybe someone else can find it useful?
I didn't work earlier with FiFos, so it was good for me with not much infos on that topic...
Thanks
🙂
 
yes, usefull for the peeps, thanks for the pdf @Zoran .

@ThorstenL , okay,, so there is still a second clock domain (MCLK), at least (only?) for the final slewrate limiters and their final clocking just before the 4 inputs of the TDA1541A ? 74AUC1Gxx in lieu of the 74F for the final signal conditioning (with the proper flying attenuation resitors, targett 0.8 to 1.2V something at the input of the TDA?)

Will wait the final shematic to understand more about how is clocked the logic ICs.

I have still the PCB design in Kickad with the new way of decoupling (-15V to Agnd & -5V, etc) but just stopped in between the isolators in front of the raptorlightning FGPA, due partially to the continuous measurements of icsazar member discoveries. Btw LM317 can be perhaps updated with some of the super LM317 reg developped on that forum (evee, trilu, etc, members) cause sourcing Elna super caps is difficult outside Thailand.... but it is off topic, sorry for that) now we know more low noise powersupply is needed... or update the shematic for simplier integrated power ic !

I go back in popcorn mode...
 
Then 2 other FiFo input lines will be empty...

I repeat:

D0 -> LE
D1 -> DL
D2 -> DR
D3 -> Control or unused

This is for the 32 Bit (BCK) long FIFO that feeds TDA1541.

The Data splitter uses only D0. Other lines are not used.

Probably it can be done just with 2 FIFO iCs

Yes, but then the flow control becomes complex. By making the Output FIFO 32 Bit we have a very simply control logic.

But it depends how long FIFO can sustains the data before Output clock is appeared and output Enable is ON, and data released?

The FIFO can hold data indefinitely. It will wait for the output clock.

No the LE from "FIFO FULL output would not be in the same place as original LE.

The FIFO delay for a bit to ripple through from input all the way to final position is 180nS. This is for the FIFO empty. So around 11nS for 1 bit to shift out after the falling edge of BCK.

Our FIFO will never be empty, so the time to refresh the output is actually immaterial as long as it shorter the the shortest BCK Cycle.

As we are only concerned about flow control of data some timing imprecision doesn't matter.

It already present on the sch I posted few posts before, (use F-F instead of shift register)

Yes, I noticed.

Did you look at my timing diagrams and check.against datasheets to see if you agree that my interpretations are right?

Just to be clear, again the proposed flow for one word:

WCK is delayed 1 BCK

WCK -> L

BCK to FIFO #0 SI, clock 16 bit's into FIFO#0, FF line goes high

WCK -> H

BCK to FIFO #0 SO, clock 16 bit out of FIFO #0, time aligned with the 16 MSB on IIS Data, inverting MSB for FIFO Data and IIS Data and creating a "MSB" marker that becomes LE, FE line goes high

BCK to FIFO #1 SI, clock 16 bit into FIFO #1, as FIFO #0 indictates FE stop clock

BCK/4 to FIFO #1 SO, clock out 16 bit and LE pulse.

We may need an additional set of latches at the output, or not. For now I want to get the flow control between the FIFO IC's right.

Thor
 
Btw LM317 can be perhaps updated with some of the super LM317 reg
I think that is the thing to avoid? Because it was used for decades in 99.9% designs. Just because it is small and easy to use without much additional elements... But it gave the sound signature. So the true sound of TDAs is without LM and SAA
🙂
Go for discrete with shunt end near the dac. It was elaborated in TDA topic 🙂.
 
yes, usefull for the peeps, thanks for the pdf @Zoran .
Hi thanks
Take a look at the first few pages when explaining the purpose of cascading F-Fs
That is actually recklocking line... Most of the people insists for just one F-F.
But actually 2 is some minimum. Or even more. There is a measurement of 3 stage F-F.
(For our purpose 2 to 4 is better. I am using 2 F-F but I will try with 4 x F-F serial for each digital line.)
 
Take a look at the first few pages when explaining the purpose of cascading F-Fs
That is actually recklocking line... Most of the people insists for just one F-F.

And if you have a known phase relationship between the reclock-clock and the clock or data you are reclocking (way too many times the word clock, this not horology), all you need is one.

Not the IF part.

But actually 2 is some minimum. Or even more. There is a measurement of 3 stage F-F.

Depends. One is the Minimum and requires a fixed pase/delay between the two clocks/signals, plus the reclock-clock must be 2 X of the signal being reclocked.

I never needed more than one for absolutely reliable operation.

For our purpose 2 to 4 is better.

I disagree. For our purpose of reclocking LE with BCK a single FF is ideal.

Thor
 
Ok, I just re-checked and TI no longer has stock of current production 40105.

1743358008822.png


Mouser has some stock, but not that much either.

1743358114465.png


So that kinda nixes that. Unless TI makes another big batch soon. I'll stop work for now.

Thor
 
I'd be willing to help here if you wanted? TI has them in stock here in the USA. I can order some and send them to you? Let me know PM if interested!

At the moment both mouser and TI have some stock. So just for my own use this is fine. Actually for my own use anything is fine, Bohrok's CPU, Raptorlightning's FPGA and so on.

But I have a specific goal that I'd like to see come out of all of this.

That is a open source PCB that can be fabbed at JLCPCB or a similar PCB/PCBA facility in Scheena, with all SMD parts fitted.

Space for Amanero style USB, space for a CS8412 DIL SPD RX to be used with the available CS8412 adapters available on Ali etc. and a "veroboard" area for other input options.

Including space for super capacitors, 3-Pin Regulators or all sorts of "upgrades" and an analogue stage daughter board with perhaps the discrete design we arrived as default, or perhaps an OPA design build in, with the rest an optimised TDA1541A.

I want the design to be simple, relatively easily understood, amenable to trouble shooting, something really suitable to DIY and much, much superior to all that garbage on Ali/Ebay.

The idea is that someone can buy a CD-Player or Chip, order up a board and get to a working DAC with the ability to customise inputs, outputs and power supplies as needed, but a highly optimised TDA1541 section (as much as we can do in context).

One thing this means no difficult to source SMD parts, actually other than TDA1541 no difficult to source parts. And no

So I rather pass USB via SPDIF (separate MCK feed) and set the SPDRX to 16 Bit IIS slave mode with BCK = 32 X FS as a compromise. This will be supportable with CS8416/DP7416 likely for another decade. My only issue is that CS8416 needs software, UNLESS I can run it in slave mode with a 32 X FS BCK and get 16 Bit + 16 Bit. Need to order an 8416 Module, one of those 8 X fake TDA1387 Boards and some 74AC74 and test it on veroboard.

If we find 74HC40105 is not on a soft-kill EOL, but remains a volume product, I'm totally gonna resume and roll this in.

Thor
 
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I was just trying to be helpful here. You are the brains behind this project and I deeply respect your knowledge and also trying to help make this tda1541 dac progress into something of high-end SQ!

I'm hoping that all will work out how you want it to be. I do know that Brijac is also willing to help out with designing the PCB once your design is ready to be put on PCB.

Please feel free to DM me if I can be of any assistance.
 
Nah, use supercapacitors.
OK, but should be tested with shunt-end PS concept for sound.

I never needed more than one for absolutely reliable operation.
metastability...
I never needed more than one for absolutely reliable operation.
I disagree. For our purpose of reclocking LE with BCK a single FF is ideal.
Recklock ALL with MCK - not with BCK.
In normal I2S stream we have 4 cycles of MCK in one BCK cycle.
that is 8 time stripes in one BCK. When ew use just one F-F we have 1:7 ratio and BCK comes out with half of MCK cycle with oposite edge...
When we use 2 F-F ratio of time in one BCK is 2:6 so it is better.
But maybe the best situation is to have 4:4 ratio of time, same rising egdges in the middle of BCK
.
BCK is too low freq for use as clock for recklocking - almost no sense...
Much better is to use MCK that is already present.
When You recklock with one F-F Q on the F-F will be "delayed" 1/2 of CLK input and in oposite rise/fall direction...
.
There is no neeed for recklocking in the output of FiFo
.
But there is for the input side.