Simplistic mosFET HV Shunt Regs

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#5,221
johnmarkp said:
Salas,

In message 4493 you say that Q4 should measure in the kilo Ohm range. When I test it from E to B, it is always in the mega ohm range. Am I testing it correctly? To my untrained eye, looking at the schematic the mega ohm range should be correct.
I do get the expected reading for Q5.
I need around 80 to 90ma, I believe that this is within the operating range for the PS.
I am having trouble getting the IRF840. Does the Gate Charge (Vgs) matter?

Thanks John
Click to expand...

In the "hundreds of kilo Ohm" I read in that message. So I just checked again with the Fluke's red probe on pin one and the black on pin three. The reading is 452k. I don't know, maybe there is difference between transistor samples. Check that your Q4's printed side faces R8 indeed.
Vgs is the voltage between gate and source. It matters for R8 value so to make for ~2mA bias for the BJTs.
 
#5,225
yes, using two isolated secondary windings.

If your HV is particularly high, then you should check with the transformer manufacturer what the maximum winding to winding voltage can be.
For an EI with separated secondary bobbins this may not be an onerous condition. For a toroid with adjacent turns between windings, this could be very onerous.
 
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#5,227
primary to secondary is not your problem. That is the problem of the manufacturer. Toroidy will get that right.

You asked
Is it possible to stack up two SSHV2 on top of each other (like two Reflectors D) and get -/+ voltage?
Click to expand...
That could put adjacent turns in the secondaries @ ~ twice the secondary voltage apart.
If you had a 0-150, 0-150Vac dual secondary, you can have 300Vac (426Vpk) between turns.

In normal use a single layer secondary on a toroid will have only 1Vpk between turns.
Do you see the problem?
 
#5,228
AndrewT said:
primary to secondary is not your problem. That is the problem of the manufacturer. Toroidy will get that right.

You askedThat could put adjacent turns in the secondaries @ ~ twice the secondary voltage apart.
If you had a 0-150, 0-150Vac dual secondary, you can have 300Vac (426Vpk) between turns.

In normal use a single layer secondary on a toroid will have only 1Vpk between turns.
Do you see the problem?
Click to expand...

Hymn,
So I understand that in case toroids are used the conclusion here is to use two separate 0-150V toroid trafos as best.
 
#5,231
Hello,

I spiced some mods in order to get 550V 41mA on output.
I changed Q3 with IRFBE30, Q4 Q5 by KSA1156 O or Y, R8 2.2k and R9 R10 @ 100k.

No change on the CCS except R5 lowered to 4.7 maybe due to the DN2540 model's different Gm.

KSA1156 looks to be a good match to KSA1381 with higher VCEO.

Only doubt is about Q3, at 20mA spare current it dissipates around 9W, need of a big 1.8C/W dissipator where space is counted. So as the amp topology is almost symmetric and AC variation is below 2mA, I wondered what was the minimum current headroom to keep on the shunt part.

From simulation 2SK117 and KSA1156 draw 4.6mA and it looks like 15mA overall would be OK. That would be 10mA in Q3 @ 5.5W. With a not too big 3C/W heatsink that should be OK.

I still have a doubt about the choice of Q3 : IRFBE30 or IRFPE50, both with a VDS 800V but the first one has an input capacitance similar to IRF840 while transcondunctance is halved and the second one has Gm slightly higher than IRF840 but an input capacitance more than doubled.
Is there any important parameter that I have overlooked ?


Cheers
Laurent
 
#5,232
The more spare current the less Zout but it can still work with further Iccs economy when the thermals are pressing. Though in more moderate spec.

Gm affects the same thing i.e. Zout (the more Gm the less Zo for same Id) but the capacitance penalty can lead to instability so it either takes open loop simulation analysis or practical lower voltage level safe testing with the oscilloscope.

One other parameter to remember is that the Vref resistors must be chosen not only high enough in value but in wattage also so to can reach and sustain your elevated Vout goal.

You should also always calculate the current margins between load and spare for the dynamic load swing, not just for its idle bias. Any Class A circuit can swing double its current bias before clipping.
 
#5,233
Salas said:
........... Any Class A circuit can swing double its current bias before clipping.
Click to expand...
Any ClassA circuit can swing double it's current bias before leaving ClassA. This only applies to push pull ClassA. And after it has left ClassA it can swing even more current.

A single ended ClassA circuit swings upto the bias current in one direction but is nearly unlimited in the other direction.
 
#5,236
Salas said:
You should also always calculate the current margins between load and spare for the dynamic load swing, not just for its idle bias.
Click to expand...
As told, probably not clearly enough, there's a mere 2mA swing at full modulation due mostly to the input stage. The following stages draw a constant current whatever the modulation (kind of pentode CCS) and/or are symmetric. The output stage has a separate supply.
I'll try between 10 to 15mA spare current, I'm ready to give away some perfs.

Salas said:
the capacitance penalty can lead to instability so it either takes open loop simulation analysis or practical lower voltage level safe testing with the oscilloscope.
Click to expand...

I'll do both I guess. Just wonder if the transistor models gathered here and there are reliable enough for that kind of analysis. I'll be able to answer that after having tried. 🙂

Thank you Salas for the point out.

Laurent
 
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