Naturally it'll make the jitter worse, simply because all transformers have leakage inductance which is responsible for their upper limit on bandwidth. To understand the magnitude of this effect you could do worse than dig out a copy of the AES paper 'Is the S/PDIF interface flawed?' authored by Chris Dunn and Malcolm Hawksford.
AES E-Library Is the AES/EBU/SPDIF Digital Audio Interface Flawed?
AES E-Library Is the AES/EBU/SPDIF Digital Audio Interface Flawed?
...and lowering the lower bandwidth limit needs a larger transformer, which inevitably has more interwinding capacitance and therefore less isolation...
Yep that's the inevitable trade-off. Either worry about jitter and give up isolation by using a bifilar wound trafo, or worry about isolation by minimizing inter-winding capacitance with a split bobbin trafo and give up bandwidth and hence get more jitter.
s/pdif is not a great clock conveyor due to bandwidth limitations. But it is a great data transporter - and best in its optical incarnation thanks to isolation.
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ok so far I am very clear on how to do it..however to drive the line I am having a bit of problems. I am thinking that maybe a video opamp will do the job. However I only have a +4.2v supply (after LDO)
Huh? Why use an opamp to drive a SPDIF output?
...or use optical and WM8805, which just works...
...or use optical and WM8805, which just works...
I dont want to use optical and this circuit is after wm8805 or similar IC.
Basically I have a spidif stream that I reclock using a hi quality oscillator and flip flops. Then I want to drive the balanced/unbalanced lines..wondering what will be the best way to drive the above.
Basically I have a spidif stream that I reclock using a hi quality oscillator and flip flops. Then I want to drive the balanced/unbalanced lines..wondering what will be the best way to drive the above.
For driving S/PDIF use something cheap and effective like an HC-series logic gate with resistive output attenuator to get the correct impedance. Crystal (now Cirrus) datasheets for their S/PDIF transmitters show the resistor values.
peufeu, I've been wondering about TOSLINK jitter suppression via the WM8805. Have you seen much of an increased pass through of jitter from TOSLINK versus coaxial S/PDIF?
Copper or optical are indistinguishable when measured with my soundcard...
It's a digital Frac-N PLL, every few seconds it'll update its frequency a little bit to follow the input, but between updates frequency stays constant, so it doesn't really care about incoming jitter.
It's a digital Frac-N PLL, every few seconds it'll update its frequency a little bit to follow the input, but between updates frequency stays constant, so it doesn't really care about incoming jitter.
Toslink is lower bandwidth therefore higher jitter (if both are implemented ideal).
If real re-clocking is performed in the sink, toslink solution is preferred as it will inject less disturbances from the source. In this case, the level of jitter is not crucial as clocks are re-generated. This is however not always true for a PLL as its HP filter is often to high. This frequency don't seem to be specified in the WM8805 data spec sheet? It only specifies the jitter it adds (intrinsic).
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If real re-clocking is performed in the sink, toslink solution is preferred as it will inject less disturbances from the source. In this case, the level of jitter is not crucial as clocks are re-generated. This is however not always true for a PLL as its HP filter is often to high. This frequency don't seem to be specified in the WM8805 data spec sheet? It only specifies the jitter it adds (intrinsic).
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If you use two scope channels to look at SPDIF input and BCK output on the scope, you'll see them smoothly and very slowly slide one relative to the other... then after about a second, it updates its frequency and the signals slide the other way... then it repeats.
No idea about the corner frequency though... also, it might update its frequency more often if the source clock is less stable, which would make the corner frequency dependent on the source...
No idea about the corner frequency though... also, it might update its frequency more often if the source clock is less stable, which would make the corner frequency dependent on the source...
Also, Toslink features air gaped butt connectors, which is a recipe for optical impedance mismatching. As we know, impedance mismatching, whether galvanic or optical, induces interface jitter. I seem to recall seeing optical index matching gel being marketed somewhere for the purpose of bridging Toslink connector air gap, giving an refractive index better matching that of the fiber. In optical's favor, of course, is that it doesn't couple common-mode noise across the interface, which could otherwise induce jitter at the receiver circuitry.
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An ideal way to drive 75ohm SPDIF is to use a video OPAMP or line driver. Maxim makes a plethora of options.
Now this is hardly cost sensitive for mass market consumer products but is a very good 75ohm line driver.
SPDIF and AES-3 can be treated as NTSC/PAL analog video up to 96khz. You can use stock video switchers and distribution amplifiers. The only thing to watch out for using pro video amps and switches is sync tip clamping options that are no good for AES/SPDIF.
For balanced AES, yes commodity RS422/485 drivers and receivers are a good choice. I do it all the time - but they should be capacitor and transformer coupled.
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OK! So below 1khz, all jitter from the s/pdif link is passed to the DAC 🙁
Ma - where did the bass go?
Or was this with digital PLL updated every 2 seconds? Then it doesn't matter I suppose.
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