It is friendly when they are PM'ed, isn't it. Better than being blindsided without any opportunity to understand how the measurements were taken.
It's nice that you and he did measurements, no matter whether they are PM'ed or put straight in the thread. Of course it's good to know the measurement conditions.
I still don't know what device he was measuring, including under what conditions. Was it my clock board or Cestrian's? If mine, was it configured as I recommended or not? I don't understand why not just give the details. If I don't know the details then I don't know if I need to do anything about it or not.
Also, as is my usual practice I am more interested in audibility than measurements. Therefore, it helps to know if somebody's measurements are in conflict with my assessment of audibility or not. Without knowing measurement details, I don't know if somebody found a conflict or or if they didn't.
Thus, in recent conversations with Cestrian about his board design, I had to take the position that we don't know if relays are all there is to it, if one relay instead of two is really a problem depending on implementation, or how much crosstalk can be due to layout (again in terms of audibility). Also, when there is a significant bypass problem that is likely audible (although perhaps harder to measure), its hard for me to take unknown measurements as conclusive, or even helpful. They could potentially be helpful with details though.
Also, as is my usual practice I am more interested in audibility than measurements. Therefore, it helps to know if somebody's measurements are in conflict with my assessment of audibility or not. Without knowing measurement details, I don't know if somebody found a conflict or or if they didn't.
Thus, in recent conversations with Cestrian about his board design, I had to take the position that we don't know if relays are all there is to it, if one relay instead of two is really a problem depending on implementation, or how much crosstalk can be due to layout (again in terms of audibility). Also, when there is a significant bypass problem that is likely audible (although perhaps harder to measure), its hard for me to take unknown measurements as conclusive, or even helpful. They could potentially be helpful with details though.
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He wrote that it was JLsound -> pcm2dsd -> RTZ DAC. The spectrum is much better with the normal PCM2DSD configuration, so it looks like some bug in my design.
I think I violate forum rules by this post, as I asked his permission to mention that something was wrong with a spectrum he measured, but I didn't ask permission to give details.
I think I violate forum rules by this post, as I asked his permission to mention that something was wrong with a spectrum he measured, but I didn't ask permission to give details.
Anybody tried to design an pcm2dsd and dsd2pcm with P2 -> https://www.parallax.com/propeller-2/ It looks very promissing for this type of thing?
Hmm looks much better and looks like there is nothing similar to P2 concept, totaly diferent concept of everything I saw recently. Those 8 x 32bit procesors and something realy unique "central hub", did you see description for central hub?
Latest version of the combined reclocker for RTZ arrived today!
This one has all the suggestions from Mark included, bar one.
I will assemble this one at the weekend and listen/measure and report back.
Again, thanks @Markw4 for all your help.
This one has all the suggestions from Mark included, bar one.
I will assemble this one at the weekend and listen/measure and report back.
Again, thanks @Markw4 for all your help.
With a lot of help from @PJotr25 I found the error in the configuration file. There was a counter that timed the FIFO read pulses that should count from 1 to some sample-rate-dependent number, but it counted from 0 to that number, causing FIFO overflows and dropped samples. I had checked the distance between read pulses with a counter in my simulation testbench, but I had made a similar error in that counter: when the desired answer was 80 cycles, the read pulses occurred every 81 cycles, but my testbench counter reported 80...
The attachment only contains the .bit file, I will post updated source code later. Compared to version 1.1, the only change is that on line 446 of topLX9.v, teller2 <= 11'b0; has been changed into teller2 <= 11'b1;
By the way, the interpolation chain and the FIFO control only work properly when the master clock is an integer multiple of 64 times the PCM sample rate, as is normally always the case. That is not a bug, it is by design.
The attachment only contains the .bit file, I will post updated source code later. Compared to version 1.1, the only change is that on line 446 of topLX9.v, teller2 <= 11'b0; has been changed into teller2 <= 11'b1;
By the way, the interpolation chain and the FIFO control only work properly when the master clock is an integer multiple of 64 times the PCM sample rate, as is normally always the case. That is not a bug, it is by design.
Attemping to put all the information in one post, so I can easily link to it from post #1:
Attached is the .bit file and source code that puts two of my PWM8 modulators and a two-channel FIR filter in an XC6SLX9-2TQG144C (or XC6SLX9-2TQG144I, if you want it to keep working when it is freezing cold). I have gone to speed grade 2, because faster was apparently not needed and speed grade 2 is also what is used in PJotr25's and olo111's simple DSD modulator for DSC2 (a.k.a. PCM2DSD). I also managed to squeeze in an extra filter for filtering and remodulating DSD input signals. The input violates the I2S hold time specification by 0.8 ns, but that is not likely to cause any problems.
PJotr25 and Markw4 have tried it in real life. With a lot of help from PJotr25, I found and fixed a bug in the FIFO controlling part.
The idea behind the modulator is explained in https://linearaudio.net/sites/linearaudio.net/files/03 Didden LA V13 mvdg.pdf pages 32...34 (pdf pages 10...12). It's a quasi-multibit modulator of which the quantizer is dithered according to dither theory, which eliminates the frequency-modulated idle tones around half the sample rate that you have with straightforward single-bit modulators and also their intermodulation products that can otherwise end up in the audio band. You pay for that with less effective noise shaping, hence it has to work at a high bit rate. The FIR interpolation filter output is also rounded with dither (and only rounded down to 35 bit word length).
For PCM, the interpolation chain consists of an 8 times interpolating FIR filter that can be set to steep or apodizing, a zero-order hold and the fifth-order low-pass signal transfer function of the sigma-delta modulator. For remodulated DSD, a 15-tap FIR filter with triangular impulse response, zero-order hold and the fifth-order low-pass signal transfer function of the sigma-delta modulator.
It is supposed to be completely compatible with PCM2DSD, but the output is at a DSD512 rate, so reclocking with the 22.5792 MHz or 24.576 MHz is not going to work, not without double edge clocking anyway. Using the master clock as the bit clock for the DAC should work, though.
There are a couple of conditions:
-It is designed to support PCM sample rates from 8 kHz up to and including 192 kHz and DSD from DSD64 up to and including DSD512 (both 44.1 kHz- and 48 kHz-based). That is, there is no support for 384 kHz PCM.
-The input accepts word lengths up to 32 bit.
-When playing PCM, the master clock must be an exact multiple of 64 times the sample rate, as it usually always is
-The master clock must be in the range from 19 MHz to 25 MHz, the normal values are 22.5792 MHz and 24.576 MHz.
Several pins that are open on the PCM2DSD board can be made high or low to activate extra functions. They have internal pull-ups and pull-downs, so when you leave them open, everything works normally.
"mute" on pin 137: internally pulled low, high level mutes the sigma-delta modulator
"scale[1]" on pin 117: internally pulled low, high level makes sigma-delta input 12 dB more sensitive, can be useful as a debug function to check the effect of overload
"scale[0]" on pin 119: internally pulled high, low level attenuates the signal by 6 dB so you have 6 dB extra headroom for intersample overs
"notSevenofNine" on pin 9: internally pulled high, low level allows only 7 out of the 9 quantization levels
"rot" on pin 7: internally pulled high, low level stops the random rotation function
Making pins 7 and 9 low could be useful for a NRZ FIRDAC of a multiple of eight taps long, like the DSC2.5.2. You then get a normal noise-shaped PWM signal that always has at least one one and at least one zero in each eight clock cycles. The average density of low-to-high and high-to-low transitions then becomes signal-independent. The disadvantage is that you get tones around 1/8 of the master clock rate and its multiples.
"notapodizing" on pin 141: internally pulled high, making it low changes the interpolation filter into an apodizing filter (smoother roll-off).
"dsdviasd" on pin 139: internally pulled high. When high, a DSD input signal gets filtered and remodulated, when low, a DSD input signal is only resynchronized to the master clock and forwarded to the output (transparent mode).
There is also one extra output:
"iclip" at pin 115: output that goes high for a bit less than a second after an integrator clips. It indicates that an intersample overshoot is larger than the modulator can handle, so you could make scale[0] low to solve that.
Attached is the .bit file and source code that puts two of my PWM8 modulators and a two-channel FIR filter in an XC6SLX9-2TQG144C (or XC6SLX9-2TQG144I, if you want it to keep working when it is freezing cold). I have gone to speed grade 2, because faster was apparently not needed and speed grade 2 is also what is used in PJotr25's and olo111's simple DSD modulator for DSC2 (a.k.a. PCM2DSD). I also managed to squeeze in an extra filter for filtering and remodulating DSD input signals. The input violates the I2S hold time specification by 0.8 ns, but that is not likely to cause any problems.
PJotr25 and Markw4 have tried it in real life. With a lot of help from PJotr25, I found and fixed a bug in the FIFO controlling part.
The idea behind the modulator is explained in https://linearaudio.net/sites/linearaudio.net/files/03 Didden LA V13 mvdg.pdf pages 32...34 (pdf pages 10...12). It's a quasi-multibit modulator of which the quantizer is dithered according to dither theory, which eliminates the frequency-modulated idle tones around half the sample rate that you have with straightforward single-bit modulators and also their intermodulation products that can otherwise end up in the audio band. You pay for that with less effective noise shaping, hence it has to work at a high bit rate. The FIR interpolation filter output is also rounded with dither (and only rounded down to 35 bit word length).
For PCM, the interpolation chain consists of an 8 times interpolating FIR filter that can be set to steep or apodizing, a zero-order hold and the fifth-order low-pass signal transfer function of the sigma-delta modulator. For remodulated DSD, a 15-tap FIR filter with triangular impulse response, zero-order hold and the fifth-order low-pass signal transfer function of the sigma-delta modulator.
It is supposed to be completely compatible with PCM2DSD, but the output is at a DSD512 rate, so reclocking with the 22.5792 MHz or 24.576 MHz is not going to work, not without double edge clocking anyway. Using the master clock as the bit clock for the DAC should work, though.
There are a couple of conditions:
-It is designed to support PCM sample rates from 8 kHz up to and including 192 kHz and DSD from DSD64 up to and including DSD512 (both 44.1 kHz- and 48 kHz-based). That is, there is no support for 384 kHz PCM.
-The input accepts word lengths up to 32 bit.
-When playing PCM, the master clock must be an exact multiple of 64 times the sample rate, as it usually always is
-The master clock must be in the range from 19 MHz to 25 MHz, the normal values are 22.5792 MHz and 24.576 MHz.
Several pins that are open on the PCM2DSD board can be made high or low to activate extra functions. They have internal pull-ups and pull-downs, so when you leave them open, everything works normally.
"mute" on pin 137: internally pulled low, high level mutes the sigma-delta modulator
"scale[1]" on pin 117: internally pulled low, high level makes sigma-delta input 12 dB more sensitive, can be useful as a debug function to check the effect of overload
"scale[0]" on pin 119: internally pulled high, low level attenuates the signal by 6 dB so you have 6 dB extra headroom for intersample overs
"notSevenofNine" on pin 9: internally pulled high, low level allows only 7 out of the 9 quantization levels
"rot" on pin 7: internally pulled high, low level stops the random rotation function
Making pins 7 and 9 low could be useful for a NRZ FIRDAC of a multiple of eight taps long, like the DSC2.5.2. You then get a normal noise-shaped PWM signal that always has at least one one and at least one zero in each eight clock cycles. The average density of low-to-high and high-to-low transitions then becomes signal-independent. The disadvantage is that you get tones around 1/8 of the master clock rate and its multiples.
"notapodizing" on pin 141: internally pulled high, making it low changes the interpolation filter into an apodizing filter (smoother roll-off).
"dsdviasd" on pin 139: internally pulled high. When high, a DSD input signal gets filtered and remodulated, when low, a DSD input signal is only resynchronized to the master clock and forwarded to the output (transparent mode).
There is also one extra output:
"iclip" at pin 115: output that goes high for a bit less than a second after an integrator clips. It indicates that an intersample overshoot is larger than the modulator can handle, so you could make scale[0] low to solve that.
I forgot to add the user constraints file to the zip archive, see the attachment for a zip that includes it. OK, now the information is spread over two posts anyway, but at least they are adjacent.
Sorry to ask here but I think it is here people knows the most so I appologize in advance : is JLSound board is using a form of stop clock ?
I am building RTZ dac with I2SoverUSB ,PCM2DSD board,Markw4's general purpose clock board and reclocker.
I am wondering how many transfers I need.
+5v pc side I2SoverUSB ---1
+5v clean side I2SoverUSB ---2
+5v clock board ---3
+3.3v reclocker board--4
+/-15v RTZ --5
+5v RTZ --6
+/-15v bohrok's filter --7
Ok,which transformer can be shared?
Triad split bobbin transformer looks nice and cheap for +5v(10v sec will be 8.6v in my country 100v wall tap)
https://www.mouser.jp/ProductDetail/Triad-Magnetics/VPP20-1000?qs=%2BfhPKvh1fqO/2G8mzo4C8g==
I am wondering how many transfers I need.
+5v pc side I2SoverUSB ---1
+5v clean side I2SoverUSB ---2
+5v clock board ---3
+3.3v reclocker board--4
+/-15v RTZ --5
+5v RTZ --6
+/-15v bohrok's filter --7
Ok,which transformer can be shared?
Triad split bobbin transformer looks nice and cheap for +5v(10v sec will be 8.6v in my country 100v wall tap)
https://www.mouser.jp/ProductDetail/Triad-Magnetics/VPP20-1000?qs=%2BfhPKvh1fqO/2G8mzo4C8g==
Well, I personally put the PCM2DSD and the I2SoverUSB clean side on the same 5v supply. Separate 5v supplies for clock/reclocker and RTZ 5v supply. Separate +/- 15v for the RTZ and the filter. Obviously separate supply for the USB supply to I2SoverUSB.
For 5v supplies I used LDOs to the RTZ and clock and LM317s to the I2SoverUSB / PCM2DSD.
For 5v supplies I used LDOs to the RTZ and clock and LM317s to the I2SoverUSB / PCM2DSD.
Hi @Cestrian
Wasn't focused on it before, but I see some of the pads for bypass caps are of different sizes. Does that mean you are planning to use a mix of ceramic and film? If so, how did you decide which to use in each location?
Cheers,
Mark
Hi Mark,
No, the only ones I overlapped are the two footprints for the power supply input and output caps so that someone with deep pockets could use the MU ones and if cost is an issue could use 1210 types. Personally my pockets are less deep than they were but I went for the acrylics - just to see. 😎
v13 is now up and running! I managed to get the text wrong on the DSD On / Mute connections and one bad solder joint on a u.fl connector but apart from that (and the mounting holes being obstructed by the PCM2DSD) it seems to work great. I will let it bed in for some hours before putting it on test.
I'll send you v14 archive and then will get that one made for my 2nd DAC.
Cheers,
Tony
ps - not fitted the LDO load res yet. I have 100R, 50R and 20R to try. Will do that once I have measurements/listening tests.
No, the only ones I overlapped are the two footprints for the power supply input and output caps so that someone with deep pockets could use the MU ones and if cost is an issue could use 1210 types. Personally my pockets are less deep than they were but I went for the acrylics - just to see. 😎
v13 is now up and running! I managed to get the text wrong on the DSD On / Mute connections and one bad solder joint on a u.fl connector but apart from that (and the mounting holes being obstructed by the PCM2DSD) it seems to work great. I will let it bed in for some hours before putting it on test.
I'll send you v14 archive and then will get that one made for my 2nd DAC.
Cheers,
Tony
ps - not fitted the LDO load res yet. I have 100R, 50R and 20R to try. Will do that once I have measurements/listening tests.