Wondering if anyone is using this output stage?
Thinking about combining the +/- with the output transformer used by DSC3.
Thinking about combining the +/- with the output transformer used by DSC3.
Can you please recommend a commercial available transformer?
Those were preferred over LL1684 by both Pavel and Andrea Ciuffoli.
Those were preferred over LL1684 by both Pavel and Andrea Ciuffoli.
You would need custom transformers from a top manufacturer or you will just make the dac sound more distorted than it should.
Complete layout change (and more) for v12!
Thankyou Mark for all your advice and for checking the design over in depth and making recommendations! I have enjoyed the experience and have learnt a lot I hope! I'm not saying it is the ultimate but there is a limit to the amount of time that can be spent. 🙄
Almost ready for upload to JLC I think!
Watch this space!
Thankyou Mark for all your advice and for checking the design over in depth and making recommendations! I have enjoyed the experience and have learnt a lot I hope! I'm not saying it is the ultimate but there is a limit to the amount of time that can be spent. 🙄
Almost ready for upload to JLC I think!
Watch this space!
PM sent.
Tony and I have been talking about thinking a lot in terms of currents rather than mainly just about voltages. It can take some getting used to.
Tony and I have been talking about thinking a lot in terms of currents rather than mainly just about voltages. It can take some getting used to.
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The dac output impedance is around 450R. Its output swing is roughly around 2v Peak to Peak most of the time, but maximum output is from 0 to +5v. Driven that that source impedance and signal level, the transformer should .1dB from 10Hz to ~80khz, with extended bandwidth to ~150kHz or so. Distortion .001% or less over the specified bandwidth. It can be done, but its not easy nor cheap. Problem is that the dac is well capable of such performance. If the transformer is going to let the dac quality shine through, then the transformer needs to be as transparent as possible.
With opa1632 stage, the source impedance is much lower, while 0.001% distortion can be very hard I guess, measurement from Ivan's D46, THD 0.0032%/THD+N 00049%
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If you are using an OPA1632 output stage in differential mode, then all bets are off. No point in using a transformer after that, IME the sound is already half-ruined.
I have said it before, but we all know there is this theory about common mode noise/distortion being a big deal and we can fix it using differential output. Except if you try SE properly it sounds way better. What it means is that our model of what is going on in the dac and or our model of human perception is too oversimplified. Since at this time we don't have a more sophisticated model, the standard approach is to ignore people who question the model and just go with the model we have. Well, if we are competing for best sound, that's fine with me. I will win. However, I am not here to beat my friends in a competition. I want them to try things for themselves and form their own opinions.
I have said it before, but we all know there is this theory about common mode noise/distortion being a big deal and we can fix it using differential output. Except if you try SE properly it sounds way better. What it means is that our model of what is going on in the dac and or our model of human perception is too oversimplified. Since at this time we don't have a more sophisticated model, the standard approach is to ignore people who question the model and just go with the model we have. Well, if we are competing for best sound, that's fine with me. I will win. However, I am not here to beat my friends in a competition. I want them to try things for themselves and form their own opinions.
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Wondering what's extra benefit to add 1:1 transformer after DC blocking capacitor for SE output?
By the way is the direct output from the DAC board very low like 500mv?
By the way is the direct output from the DAC board very low like 500mv?
The direct output is from switched 5v. If it were an NRZ dac the peak to peak output might be around 2.5v. Since its RTZ it will be less, maybe half that.
For my dac the DC blocking cap and transformer are the output stage. After that there is no more measurable RF, just audio. IOW, the transformer makes a pretty good passive RF filter.
For my dac the DC blocking cap and transformer are the output stage. After that there is no more measurable RF, just audio. IOW, the transformer makes a pretty good passive RF filter.
Attached is the result of my attempt to put two of my PWM8 modulators and a two-channel FIR filter in an XC6SLX9-2TQG144C (or XC6SLX9-2TQG144I, if you want it to keep working when it freezes). I have gone to speed grade 2, because faster was apparently not needed and speed grade 2 is also what is used in PJotr25's and olo111's simple DSD modulator for DSC2 (a.k.a. PCM2DSD). I also managed to squeeze in an extra filter for filtering and remodulating DSD input signals. The input violates the I2S hold time specification by 0.8 ns, but that is not likely to cause any problems.
I haven't tried it in real life, I have only run some simulations. I have neither an Amanero or similar board nor a PCM2DSD.
It is supposed to be completely compatible with PCM2DSD, but the output is at a DSD512 rate, so reclocking with the 22.5792 MHz or 24.576 MHz is not going to work, not without double edge clocking anyway. Using the master clock as the bit clock for the DAC should work, though.
Several pins that are open on the PCM2DSD board can be made high or low to activate extra functions. They have internal pull-ups and pull-downs, so when you leave them open, everything works normally.
"mute" on pin 137: internally pulled low, high level mutes the sigma-delta modulator
"scale[1]" on pin 117: internally pulled low, high level makes sigma-delta input 12 dB more sensitive, can be useful as a debug function to check the effect of overload
"scale[0]" on pin 119: internally pulled high, low level attenuates the signal by 6 dB so you have 6 dB extra headroom for intersample overs
"notSevenofNine" on pin 9: internally pulled high, low level allows only 7 out of the 9 quantization levels
"rot" on pin 7: internally pulled high, low level stops the random rotation function
Making pins 7 and 9 low could be useful for a NRZ FIRDAC of a multiple of eight taps long, like the DSC2.5.2. You then get a normal noise-shaped PWM signal that always has at least one one and at least one zero in each eight clock cycles. The average density of low-to-high and high-to-low transitions then becomes signal-independent.
"notapodizing" on pin 141: internally pulled high, making it low changes the interpolation filter into an apodizing filter (smoother roll-off).
"dsdviasd" on pin 139: internally pulled high. When high, a DSD input signal gets filtered and remodulated, when low, a DSD input signal is only resynchronized to the master clock and forwarded to the output (transparent mode).
There is also one extra output:
"iclip" at pin 115: output that goes high for a bit less than a second after an integrator clips. It indicates that an intersample overshoot is larger than the modulator can handle, so you could make scale[0] low to solve that.
Could someone please program the .bit file into a PCM2DSD board to see if it really works?
I haven't tried it in real life, I have only run some simulations. I have neither an Amanero or similar board nor a PCM2DSD.
It is supposed to be completely compatible with PCM2DSD, but the output is at a DSD512 rate, so reclocking with the 22.5792 MHz or 24.576 MHz is not going to work, not without double edge clocking anyway. Using the master clock as the bit clock for the DAC should work, though.
Several pins that are open on the PCM2DSD board can be made high or low to activate extra functions. They have internal pull-ups and pull-downs, so when you leave them open, everything works normally.
"mute" on pin 137: internally pulled low, high level mutes the sigma-delta modulator
"scale[1]" on pin 117: internally pulled low, high level makes sigma-delta input 12 dB more sensitive, can be useful as a debug function to check the effect of overload
"scale[0]" on pin 119: internally pulled high, low level attenuates the signal by 6 dB so you have 6 dB extra headroom for intersample overs
"notSevenofNine" on pin 9: internally pulled high, low level allows only 7 out of the 9 quantization levels
"rot" on pin 7: internally pulled high, low level stops the random rotation function
Making pins 7 and 9 low could be useful for a NRZ FIRDAC of a multiple of eight taps long, like the DSC2.5.2. You then get a normal noise-shaped PWM signal that always has at least one one and at least one zero in each eight clock cycles. The average density of low-to-high and high-to-low transitions then becomes signal-independent.
"notapodizing" on pin 141: internally pulled high, making it low changes the interpolation filter into an apodizing filter (smoother roll-off).
"dsdviasd" on pin 139: internally pulled high. When high, a DSD input signal gets filtered and remodulated, when low, a DSD input signal is only resynchronized to the master clock and forwarded to the output (transparent mode).
There is also one extra output:
"iclip" at pin 115: output that goes high for a bit less than a second after an integrator clips. It indicates that an intersample overshoot is larger than the modulator can handle, so you could make scale[0] low to solve that.
Could someone please program the .bit file into a PCM2DSD board to see if it really works?
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Hi Marcel,
The existing PCM2DSD requires a 22/24MHz MCLK input signal. Does your version require 45/49MHz on the same pin?
Mark
The existing PCM2DSD requires a 22/24MHz MCLK input signal. Does your version require 45/49MHz on the same pin?
Mark
Practical accessing of the added control pins may require a new layout of the PCM2DSD board. So far no schematic has been published for it, although a schematic can probably be inferred from inspection of the gerbers and the BOM.
Is that in reference to the circuit freezing up (hanging), or to ambient temperature?