You could solder thin enamelled copper wires with the isolation scratched off the end to the extra pins. I've done that before with SRC4392 status outputs (also 0.5 mm pitch). I've tried to choose the pins such that there is always an unused pin in between the ones that are used, to reduce the chance of shorts.
Its still pretty early in the morning here. A little later I will try loading the bit file, then try a simple setup to look at the outputs with a scope. If that works, then maybe try connecting to the added input pins. If all that looks good then maybe rearrange things to try it with the dac.
I just realized that the FIFO depth is a bit marginal. I wanted a depth of twice the number of samples it has to store, but forgot that left and right are multiplexed.
Version 1.1 with the longer FIFO. Only the changes with respect to the version of post #3595 (longer FIFO, updated FIFO name) and the new bit file are in the .zip.
Just to be clear, the default values that you get when the new FPGA input pins are left open are the settings that I expect to work best with the DAC of this thread. The other options are mostly meant for DSC2 DACs, for debugging and for recordings with unusually large intersample overshoots.
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Having some trouble here copying Marcel's FPGA files to Oracle Virtual Box (where Impact is). Right now the only method is to share the CD drive, which for some reason isn't working properly. Probably have to set up a network file share between Linux and Windows before I can proceed further.
Here we go:
Don't have short ground leads hooked up yet. This is the output of PCM2DSD while playing music.
A little more close up:
Don't have short ground leads hooked up yet. This is the output of PCM2DSD while playing music.
A little more close up:
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There are 4 micro-clips I can use for testing input pins. Here are couple of them (little hairs are from alcohol wipes to help remove flux):
Nice tools! The effect of grounding both notSevenofNine (pin 9) and rot (pin 7) should be clearly observable on an oscilloscope. You should then see a new pulse starting precisely every eight clock cycles, rather than randomized.
It probably means I misremembered what edges are happening every eight cycles, but I will have a look at my Verilog code anyway.
Everything is fine except my memory. I looked in pwm.v and it is supposed to work exactly like this: falling edges every eight cycles when notSevenofNine and rot are low.
@PJotr25 has been so friendly to do some spectrum measurements and PM them to me. They look reasonable at very low signal levels, but awful at high signal levels, with lots of distortion products, not necessarily at harmonics. He used version 1.1 (version 1 was just as bad) and checked whether clocking the DAC with the master clock made any difference; it reduced the noise floor, but not the distortion.
Most of the simulations I did were behavioural simulations with a zero or DC input. The spectrum always looked good in those, but then again, so do PJotr25's measurements at low levels and 0 is a very low signal level. I will update the simulation testbench and see if I can find the issue.
Apologies for the inconvenience and to be continued...
Most of the simulations I did were behavioural simulations with a zero or DC input. The spectrum always looked good in those, but then again, so do PJotr25's measurements at low levels and 0 is a very low signal level. I will update the simulation testbench and see if I can find the issue.
Apologies for the inconvenience and to be continued...