Hi everyone,
I got some PMs from Mark about a bug in the DSD remodulating mode of my PCM2DSD configuration files. He gets excessive noise and about 3 % second harmonic distortion on the right channel (at 100 Hz, 1 kHz or 10 kHz, 0 dB DSD), the left channel is not affected.
Did anyone else notice misbehaviour of one channel in the DSD remodulating mode and if so, what channel and what misbehaviour?
Regarding Mark's observations, when playing PCM, both channels work normally, and there is also no problem when playing DSD in the transparant mode (dsdviasd forced low). The excessive noise only occurs on the right channel when playing DSD with dsdviasd high (or open).
There is excessive noise at all DSD rates Mark tried, including DSD64. There is no excessive noise when playing .dsf files with periodic patterns that have no out-of-band quantization noise. I suspect that some bug in my design causes the second-order distortion, as well as audio-frequency intermodulation products between out-of-band quantization noise of the incoming DSD signal.
Mark used a fully isolated I2SoverUSB board.
Best regards,
Marcel
I got some PMs from Mark about a bug in the DSD remodulating mode of my PCM2DSD configuration files. He gets excessive noise and about 3 % second harmonic distortion on the right channel (at 100 Hz, 1 kHz or 10 kHz, 0 dB DSD), the left channel is not affected.
Did anyone else notice misbehaviour of one channel in the DSD remodulating mode and if so, what channel and what misbehaviour?
Regarding Mark's observations, when playing PCM, both channels work normally, and there is also no problem when playing DSD in the transparant mode (dsdviasd forced low). The excessive noise only occurs on the right channel when playing DSD with dsdviasd high (or open).
There is excessive noise at all DSD rates Mark tried, including DSD64. There is no excessive noise when playing .dsf files with periodic patterns that have no out-of-band quantization noise. I suspect that some bug in my design causes the second-order distortion, as well as audio-frequency intermodulation products between out-of-band quantization noise of the incoming DSD signal.
Mark used a fully isolated I2SoverUSB board.
Best regards,
Marcel
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Again attemping to put all the information in one post, so I can easily link to it from post #1:
Thanks to Markw4, who found that there was a problem and who did lots of experiments to help locate it, the bug that caused excessive noise and distortion in the right channel when remodulating DSD with my alternative PCM2DSD configuration files has been solved. The original memory-based DSD filter, which had a dubious clock transition and a rather complicated multiplexing scheme between left and right, has been replaced with two straightforward canonical signed digit/non-adjacent form FIR filters. Mark still prefers the latest of PJotr25's configuration files over mine, but everyone who likes to can try it for themselves.
Attached are the .bit file and source code for version 1.5, which has the fix for the DSD filter bug, and is otherwise similar to version 1.4. The .bit file puts two of my PWM8 modulators, a two-channel interpolating FIR filter and two filters for remodulating DSD in an XC6SLX9-2TQG144C (or XC6SLX9-2TQG144I, if you want it to keep working when it is freezing cold). This is the same type of FPGA as used in PJotr25's and olo111's simple DSD modulator for DSC2 (a.k.a. PCM2DSD). The input violates the I2S hold time specification by 0.8 ns, but that is not likely to cause any problems.
Besides the bug fix, version 1.5 is the same as version 1.4, which means it features a switchable dither order for all three (re-)quantizers (rounding stages) in the design. According to dither theory, the first n moments of the quantization error can be made independent of the signal by adding n uniformly distributed random signals of 1 LSB peak-peak (1 LSB after requantization, that is) to the signal before rounding. n defaults to 2, but you can make it 1, 3 or 4 by grounding the correct input pins.
The idea behind the modulator is explained in https://www.diyaudio.com/community/attachments/03-didden-la-v13-mvdg-pdf.1389425/ pages 32...34 (pdf pages 10...12). It's a quasi-multibit modulator of which the quantizer is dithered according to dither theory, which eliminates the frequency-modulated idle tones around half the sample rate that you have with straightforward single-bit modulators and also their intermodulation products that can otherwise end up in the audio band. You pay for that with less effective noise shaping, hence it has to work at a high bit rate. The FIR interpolation filter output is also rounded with dither (and only rounded to 35 bit word length).
For PCM, the interpolation chain consists of an 8 times interpolating FIR filter that can be set to steep or apodizing, a zero-order hold and the fifth-order low-pass signal transfer function of the sigma-delta modulator (5th order Butterworth at 176 kHz or 192 kHz). For remodulated DSD, the filter chain consists of a 15-tap FIR filter with triangular impulse response, a zero-order hold and the fifth-order low-pass signal transfer function of the sigma-delta modulator.
The .zip also contains FIR filter impulse and frequency response plots. The horizontal axis is in samples after 8 times interpolation for the impulse responses. For the frequency responses, 0.125 on the horizontal scale corresponds to the input sample rate, the vertical scale is in dB. The zero-order hold and sigma-delta signal transfer function are not included.
The design is supposed to be completely compatible with PCM2DSD, but the output is at a DSD512 rate, so reclocking with the 22.5792 MHz or 24.576 MHz is not going to work, not without double edge clocking anyway. Using the master clock as the bit clock for the DAC should work, though.
There are a couple of conditions:
-It is designed to support PCM sample rates from 8 kHz up to and including 192 kHz and DSD from DSD64 up to and including DSD512 (both 44.1 kHz- and 48 kHz-based). That is, there is no support for 384 kHz PCM.
-The input accepts word lengths up to 32 bit.
-When playing PCM, the master clock must be an exact multiple of 64 times the sample rate, as it usually always is
-The master clock must be in the range from 19 MHz to 25 MHz, the normal values are 22.5792 MHz and 24.576 MHz.
Several pins that are open on the earlier PCM2DSD boards can be made high or low to activate extra functions. The latest PCM2DSD boards make most of these pins easily accessible. The pins have internal pull-ups and pull-downs, so when you leave them open, everything works normally.
"ndithord1" on pin 1, "ndithord3" on pin 41, "ndithord4" on pin 27: internally pulled high, making one and only one of these low changes the dither order n from 2 to 1, 3 or 4, respectively.
"mute" on pin 137: internally pulled low, high level mutes the sigma-delta modulator
"scale[1]" on pin 117: internally pulled low, high level makes sigma-delta input 12 dB more sensitive, can be useful as a debug function to check the effect of overload
"scale[0]" on pin 119: internally pulled high, low level attenuates the signal by 6 dB so you have 6 dB extra headroom for intersample overs
"notSevenofNine" on pin 9: internally pulled high, low level allows only 7 out of the 9 quantization levels
"rot" on pin 7: internally pulled high, low level stops the random rotation function
Making pins 7 and 9 low could be useful for a NRZ FIRDAC of a multiple of eight taps long, like the DSC2.5.2. You then get a normal noise-shaped PWM signal that always has at least one one and at least one zero in each eight clock cycles. The average density of low-to-high and high-to-low transitions then becomes signal-independent. The disadvantage is that you get tones around 1/8 of the master clock rate and its multiples.
Making notSevenofNine low also has the disadvantage that it much reduces the headroom for intersample overshoots. It might even be insufficient at 0 dBFS when the dither order is high. It could therefore be useful to try rot = 0 while leaving notSevenofNine open, when you use a DSC2.5.2.
"notapodizing" on pin 141: internally pulled high, making it low changes the interpolation filter into an apodizing filter (smoother roll-off, shorter impulse response).
"dsdviasd" on pin 139: internally pulled high. When high, a DSD input signal gets filtered and remodulated, when low, a DSD input signal is only resynchronized to the master clock and forwarded to the output (transparent mode).
There is also one extra output:
"iclip" at pin 115: output that goes high for a bit less than a second after an integrator clips. It indicates that an intersample overshoot is larger than the modulator can handle, so you could make scale[0] low to solve that.
Thanks to Markw4, who found that there was a problem and who did lots of experiments to help locate it, the bug that caused excessive noise and distortion in the right channel when remodulating DSD with my alternative PCM2DSD configuration files has been solved. The original memory-based DSD filter, which had a dubious clock transition and a rather complicated multiplexing scheme between left and right, has been replaced with two straightforward canonical signed digit/non-adjacent form FIR filters. Mark still prefers the latest of PJotr25's configuration files over mine, but everyone who likes to can try it for themselves.
Attached are the .bit file and source code for version 1.5, which has the fix for the DSD filter bug, and is otherwise similar to version 1.4. The .bit file puts two of my PWM8 modulators, a two-channel interpolating FIR filter and two filters for remodulating DSD in an XC6SLX9-2TQG144C (or XC6SLX9-2TQG144I, if you want it to keep working when it is freezing cold). This is the same type of FPGA as used in PJotr25's and olo111's simple DSD modulator for DSC2 (a.k.a. PCM2DSD). The input violates the I2S hold time specification by 0.8 ns, but that is not likely to cause any problems.
Besides the bug fix, version 1.5 is the same as version 1.4, which means it features a switchable dither order for all three (re-)quantizers (rounding stages) in the design. According to dither theory, the first n moments of the quantization error can be made independent of the signal by adding n uniformly distributed random signals of 1 LSB peak-peak (1 LSB after requantization, that is) to the signal before rounding. n defaults to 2, but you can make it 1, 3 or 4 by grounding the correct input pins.
The idea behind the modulator is explained in https://www.diyaudio.com/community/attachments/03-didden-la-v13-mvdg-pdf.1389425/ pages 32...34 (pdf pages 10...12). It's a quasi-multibit modulator of which the quantizer is dithered according to dither theory, which eliminates the frequency-modulated idle tones around half the sample rate that you have with straightforward single-bit modulators and also their intermodulation products that can otherwise end up in the audio band. You pay for that with less effective noise shaping, hence it has to work at a high bit rate. The FIR interpolation filter output is also rounded with dither (and only rounded to 35 bit word length).
For PCM, the interpolation chain consists of an 8 times interpolating FIR filter that can be set to steep or apodizing, a zero-order hold and the fifth-order low-pass signal transfer function of the sigma-delta modulator (5th order Butterworth at 176 kHz or 192 kHz). For remodulated DSD, the filter chain consists of a 15-tap FIR filter with triangular impulse response, a zero-order hold and the fifth-order low-pass signal transfer function of the sigma-delta modulator.
The .zip also contains FIR filter impulse and frequency response plots. The horizontal axis is in samples after 8 times interpolation for the impulse responses. For the frequency responses, 0.125 on the horizontal scale corresponds to the input sample rate, the vertical scale is in dB. The zero-order hold and sigma-delta signal transfer function are not included.
The design is supposed to be completely compatible with PCM2DSD, but the output is at a DSD512 rate, so reclocking with the 22.5792 MHz or 24.576 MHz is not going to work, not without double edge clocking anyway. Using the master clock as the bit clock for the DAC should work, though.
There are a couple of conditions:
-It is designed to support PCM sample rates from 8 kHz up to and including 192 kHz and DSD from DSD64 up to and including DSD512 (both 44.1 kHz- and 48 kHz-based). That is, there is no support for 384 kHz PCM.
-The input accepts word lengths up to 32 bit.
-When playing PCM, the master clock must be an exact multiple of 64 times the sample rate, as it usually always is
-The master clock must be in the range from 19 MHz to 25 MHz, the normal values are 22.5792 MHz and 24.576 MHz.
Several pins that are open on the earlier PCM2DSD boards can be made high or low to activate extra functions. The latest PCM2DSD boards make most of these pins easily accessible. The pins have internal pull-ups and pull-downs, so when you leave them open, everything works normally.
"ndithord1" on pin 1, "ndithord3" on pin 41, "ndithord4" on pin 27: internally pulled high, making one and only one of these low changes the dither order n from 2 to 1, 3 or 4, respectively.
"mute" on pin 137: internally pulled low, high level mutes the sigma-delta modulator
"scale[1]" on pin 117: internally pulled low, high level makes sigma-delta input 12 dB more sensitive, can be useful as a debug function to check the effect of overload
"scale[0]" on pin 119: internally pulled high, low level attenuates the signal by 6 dB so you have 6 dB extra headroom for intersample overs
"notSevenofNine" on pin 9: internally pulled high, low level allows only 7 out of the 9 quantization levels
"rot" on pin 7: internally pulled high, low level stops the random rotation function
Making pins 7 and 9 low could be useful for a NRZ FIRDAC of a multiple of eight taps long, like the DSC2.5.2. You then get a normal noise-shaped PWM signal that always has at least one one and at least one zero in each eight clock cycles. The average density of low-to-high and high-to-low transitions then becomes signal-independent. The disadvantage is that you get tones around 1/8 of the master clock rate and its multiples.
Making notSevenofNine low also has the disadvantage that it much reduces the headroom for intersample overshoots. It might even be insufficient at 0 dBFS when the dither order is high. It could therefore be useful to try rot = 0 while leaving notSevenofNine open, when you use a DSC2.5.2.
"notapodizing" on pin 141: internally pulled high, making it low changes the interpolation filter into an apodizing filter (smoother roll-off, shorter impulse response).
"dsdviasd" on pin 139: internally pulled high. When high, a DSD input signal gets filtered and remodulated, when low, a DSD input signal is only resynchronized to the master clock and forwarded to the output (transparent mode).
There is also one extra output:
"iclip" at pin 115: output that goes high for a bit less than a second after an integrator clips. It indicates that an intersample overshoot is larger than the modulator can handle, so you could make scale[0] low to solve that.
If you don't mind me asking, what's keeping you from making noise & distortion measurements yourself?
Lack of an Amanero and a PCM2DSD in this case. I only wrote the alternative configuration file because you and Markw4 were interested in it (although you lost interest in the meantime and Mark prefers PJotr25's latest version), I never intended to use it myself. The digital sigma-delta modulator is a variant of something I do use, though, namely the sigma-delta modulator of my valve DAC.
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You expressed your interest via PM a long time ago, which means I actually violated forum rules in post #4045.
Thanks, I've moved Hans's suggestion from the "Suggestions for further improvements" to the "Variants" in post #1, as it is now a real-life variant.
Yes, when we were trying to find the cause for the issues of PCM2DSD I did ask if your quasi-bit modulator or any other similar modulator would fit the into XC6SLXS9. But not for my needs but because most were using PCM2DSD with your DAC. Not that this matters much but your post #4045 paints a slightly distorted picture.
Added Markw4's reclock board, further improved clarity.
With hqplayer at -6db, output is very low probably 100mv.
Combo384 - IanCanadaFiFoPi - Reclocker - FIRDAC - 45K Butterworth filter - DC blocking capacitor (with mute relay)
Super regulator - FIRDAC +/-15V
Salas Reflector-D - FIRDAC 5V - reclock board (3.3V)
Salas Reflector-D - FifoPi 3.3V
Super regulator - FifoPi 5V
Very nice! Is there a BOM for anyone who might like to try it? (Inductors can vary quite a bit in terms of sound.)
Just for experiment,
1.8mh RF inductor, LQH43NH182J03L from mouser, has high resistance though.
4700pf, 12063A472JAT2A from mouser,
For 15000pf, just 3x4700pf//1000pf
I used black gate N for DC blocking, tiny with very relax sound.
Output is very low, probably 100mv with hqplayer @-6db, I put a 6J51P stage (50-70x) after.
1.8mh RF inductor, LQH43NH182J03L from mouser, has high resistance though.
4700pf, 12063A472JAT2A from mouser,
For 15000pf, just 3x4700pf//1000pf
I used black gate N for DC blocking, tiny with very relax sound.
Output is very low, probably 100mv with hqplayer @-6db, I put a 6J51P stage (50-70x) after.
Rewired, shunt regulator to the FifoPi 5V and 5V super regulator to FIRDAC & reclocker. That brought back the bass.
I guess shunt regulator helps FifoPi a lot, while 5V feed to FIRDAC and reclocker board shouldn't have that much impact.
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Would like to add to what 2A3SET has recently posted. Heard a recording he made of his dac with its passive output filter and with Iancanada clocks. The recording sounded very good on my system. Therefore I would definitely recommend giving his approach a try.
Also, he used my reclocker board while bypassing the isolators. Looks to me like he did a good job of hacking it a little. Looks like this:
Also, he used my reclocker board while bypassing the isolators. Looks to me like he did a good job of hacking it a little. Looks like this: