Re: Temperature compensation for bias
Hi bawang,
Did you use the Nelson Pass method of matching your output MOSFETs or some other method? I have seen different circuits, voltages, currents and methods used. Some do one at a time. Some do waiting exactly 30 seconds. Some do running the MOSFET under test warm and attached to heatsink. Some do all the devices at same time so heatsink is same temperature all the time for all as there is residual heat when doing one at time. Some use a few different currents in the tests to know the different Vgs characters the devices may have. Some actually heat the device or heatsink to a specific temperature, i.e. 60C, 70C, and do the test. What approach, voltage(s), current(s) did you test for? I assume you only tested Vgs?
Did you do use any additional methods to even out the the bias current? Some testing methods also provide calculations to use to ad resistance to lower the Vgs of those devices higher than the lowest on the rail. Did you use any additional method to even out the bias current of your 4 output devices?
Regards,
John L. Males
Willowdale, Ontario
Canada
31 October 2007 13:10
Official Quasi Thread Researcher
bawang said:
Hi bawang,
Did you use the Nelson Pass method of matching your output MOSFETs or some other method? I have seen different circuits, voltages, currents and methods used. Some do one at a time. Some do waiting exactly 30 seconds. Some do running the MOSFET under test warm and attached to heatsink. Some do all the devices at same time so heatsink is same temperature all the time for all as there is residual heat when doing one at time. Some use a few different currents in the tests to know the different Vgs characters the devices may have. Some actually heat the device or heatsink to a specific temperature, i.e. 60C, 70C, and do the test. What approach, voltage(s), current(s) did you test for? I assume you only tested Vgs?
Did you do use any additional methods to even out the the bias current? Some testing methods also provide calculations to use to ad resistance to lower the Vgs of those devices higher than the lowest on the rail. Did you use any additional method to even out the bias current of your 4 output devices?
Regards,
John L. Males
Willowdale, Ontario
Canada
31 October 2007 13:10
Official Quasi Thread Researcher
Hi guys,
I was trying to mount the IRF840s for the NMOS200 boards and I found that the heatsink tabs of adjacent mosfets are very close (just short of touching) to each other. Will that cause a problem?
Vivek
I was trying to mount the IRF840s for the NMOS200 boards and I found that the heatsink tabs of adjacent mosfets are very close (just short of touching) to each other. Will that cause a problem?
Vivek
Hi, John. I did my matching the quick and dirty way. Same circuit as Nelson's, matched at the bias point of 50mA, for 5 seconds, no heatsinks.... Using a regulated 15V DC power supply, resistor of 220 ohms. I found out that this gave good results, with variations of less than 5mA between devices at 50mA. FETs did not heat up at all (to the touch, at least) even after being tested for 10 minutes. However, the Vgs will vary, reducing slowly. That's why I choose 5 seconds, so that I don't have to wait the whole night. All FETs are kept at the same initial temperature though, on my table top! Unmatched, variations were as large as 70mA, with the lowest reading at 7mA, highest at 77mA.....
I bought 20 IRF840s to get 2 matched sets of 4 numbers each. Quite an expensive affair....
Vivek, the tabs of the adjacent FETs are at the same potential, touching is no problem. If you check the PCB, the center pins of the FETs (connected to the tabs) are actually connected together.
I bought 20 IRF840s to get 2 matched sets of 4 numbers each. Quite an expensive affair....
Vivek, the tabs of the adjacent FETs are at the same potential, touching is no problem. If you check the PCB, the center pins of the FETs (connected to the tabs) are actually connected together.
Hi bawang,
-Chris
That sounds about right in my experience, a little better than I normally see. I do it differently and on a heat sink and yet the yield is about the same. That is unless you are matching for a Counterpoint amp. They must be matched much more closely.
-Chris
Chris, know what, I bought 3 batches of these FETs, 2 batches of ST brand and 1 batch (10 nos) of original IRF. The original IRF matches easier, giving closer numbers. The ST brand's numbers were all over the place, with Vgs from 3.9XX volts to 3.5XX volts. The original IRF's numbers were 3.5XX volts throughout. The FETs with the closer numbers may come from the same batch of products....
Now I know why BJT output stages are more popular (or so it seems), where matching is not so critical. The bias current variation (nominal value of around 50mA to 100mA) of all the BJT amps that I constructed is not more than 10mA, with NO matching whatsoever.
Now I know why BJT output stages are more popular (or so it seems), where matching is not so critical. The bias current variation (nominal value of around 50mA to 100mA) of all the BJT amps that I constructed is not more than 10mA, with NO matching whatsoever.
Hi bawang,
Well. It depends on how close you match them and if you are matching complimentary parts also. That is a pain. Parts from the same batch are the way to go for sure. But who can afford a rail or two of 25 pcs? That gets pricey, but your yield increases with the number of individuals.
-Chris
Well. It depends on how close you match them and if you are matching complimentary parts also. That is a pain. Parts from the same batch are the way to go for sure. But who can afford a rail or two of 25 pcs? That gets pricey, but your yield increases with the number of individuals.
I will agree that the yield on bipolars is much higher with good transistors. But I would say that matching is just as important with bipolars as it is for mosfets. My guess is that you are running higher bias on those so the emitter resistors do work to force a balance. Check your current balance as you lower the bias current doen to a couple mA. The emitter resistors should be less effective down there and you may see a wider spread.
Yes, that is what I was getting with IRF transistors.
-Chris
Chris,
What method do you use to match MOSFETs?
Do you think there is any merit in using different value source/gate resistor to balance the bias for output MOSFET devices? If the yield for matches is less than 50% of a lot even of same batch number it will not be practical, and actually not possible, to purchase enough devices for an active crossover based system I wish to build.
I assume the ideal is to have the positive and negative side of the rails with the same bias current for a given module, therefore same Vgs test value?
My intent for the MJE, BC and 2SC parts is to match based on Hfe. I am may just use a multimeter based one or make a jig to test at the current values quasi modules operate these at. I am not so concerned with the specific Hfe as much as the relative value to the other devices in the lot to sort for pair matching within a module. If the opportunity exists in the results I will make an effort to match as close as possible module pairs for L and R. Not a mush, but as I will have the values and sorted by values it will take no extra effort to sort based on L and R pairs where the opportunity exists, the midrange amps would be the first, then tweeters, then woofers. Likely the woofer modules would have the widest differences between modules and perhaps within as well.
I have a Polar T1000 that could cover more range and conditions to match MOSFETs and BJTs if I can figure out what is wrong with it. I have had no time to spend any time to dig into what the problem is with the Polar T1000, but if I can, or with help of someone, figure it out the T1000 should be very effective and easy to match up devices.
Regards,
John L. Males
Willowdale, Ontario
Canada
01 November 2007 01:50
Official Quasi Thread Researcher
P.S. quasi, I hope the weather is more settled in your neck of the woods. I heard there was some rough weather down your part of the world last week. jlm
What method do you use to match MOSFETs?
Do you think there is any merit in using different value source/gate resistor to balance the bias for output MOSFET devices? If the yield for matches is less than 50% of a lot even of same batch number it will not be practical, and actually not possible, to purchase enough devices for an active crossover based system I wish to build.
I assume the ideal is to have the positive and negative side of the rails with the same bias current for a given module, therefore same Vgs test value?
My intent for the MJE, BC and 2SC parts is to match based on Hfe. I am may just use a multimeter based one or make a jig to test at the current values quasi modules operate these at. I am not so concerned with the specific Hfe as much as the relative value to the other devices in the lot to sort for pair matching within a module. If the opportunity exists in the results I will make an effort to match as close as possible module pairs for L and R. Not a mush, but as I will have the values and sorted by values it will take no extra effort to sort based on L and R pairs where the opportunity exists, the midrange amps would be the first, then tweeters, then woofers. Likely the woofer modules would have the widest differences between modules and perhaps within as well.
I have a Polar T1000 that could cover more range and conditions to match MOSFETs and BJTs if I can figure out what is wrong with it. I have had no time to spend any time to dig into what the problem is with the Polar T1000, but if I can, or with help of someone, figure it out the T1000 should be very effective and easy to match up devices.
Regards,
John L. Males
Willowdale, Ontario
Canada
01 November 2007 01:50
Official Quasi Thread Researcher
P.S. quasi, I hope the weather is more settled in your neck of the woods. I heard there was some rough weather down your part of the world last week. jlm
Hello All,
I am curious if any of you have made your PCBs using the print PCB image to an injet type paper, then iron the PCB image onto the copper, et al process?
If so were you happy with the results?
Regards,
John L. Males
Willowdale, Ontario
Canada
05 November 2007 18:42
Official Quasi Thread Researcher
I am curious if any of you have made your PCBs using the print PCB image to an injet type paper, then iron the PCB image onto the copper, et al process?
If so were you happy with the results?
Regards,
John L. Males
Willowdale, Ontario
Canada
05 November 2007 18:42
Official Quasi Thread Researcher
Hi, John. You must mean "laser printer"...... I am not aware of any "inkjet (ie alcohol-based ink)" printer/paper combination that can be used.
FYI, I am using the "Press n Peel" paper with my laser printer (Canon)... Results are satisfactory IF
a) The blank PCB is EXTREMELY clean
b) Blank PCB is flat during ironing, rules out cheaper PCB base material that tends to warp
c) Careful ironing, don't press too hard as you may end up with squashed traces
Hope this helps.
FYI, I am using the "Press n Peel" paper with my laser printer (Canon)... Results are satisfactory IF
a) The blank PCB is EXTREMELY clean
b) Blank PCB is flat during ironing, rules out cheaper PCB base material that tends to warp
c) Careful ironing, don't press too hard as you may end up with squashed traces
Hope this helps.
Hi John,
I match mosfets by using a jig on a heat sink with four locations for parts. It's old school, but it works. Basically Nelson's method. The final matching is normally two or four transistors that I run together and match for gate voltage and drain current. This ensures they are all at the same temperature when the readings are taken. I use a thermocouple thermometer to read the heat sink temperature. I get very tight matches when I need them.
I will not mess around with resistor values in an effort to match currents. They will not track if you do that. I'm afraid that you simply have to do it right.
So, what to do? Define your acceptable boundaries and go through your population of parts. Drag the closest parts out and test them together on the same heat sink to match their temperatures and take your readings. The number of parts you need to buy will depend on
1.) What the spread is on that manufacturer, and
2.) How close you need them.
-Chris
I match mosfets by using a jig on a heat sink with four locations for parts. It's old school, but it works. Basically Nelson's method. The final matching is normally two or four transistors that I run together and match for gate voltage and drain current. This ensures they are all at the same temperature when the readings are taken. I use a thermocouple thermometer to read the heat sink temperature. I get very tight matches when I need them.
I will not mess around with resistor values in an effort to match currents. They will not track if you do that. I'm afraid that you simply have to do it right.
So, what to do? Define your acceptable boundaries and go through your population of parts. Drag the closest parts out and test them together on the same heat sink to match their temperatures and take your readings. The number of parts you need to buy will depend on
1.) What the spread is on that manufacturer, and
2.) How close you need them.
-Chris
bawang said:
bawang,
The process I was referring to is an alternate to the "Press n Peel" paper. The process involves a laser printer using a photographic based paper normally used in inkjet printers. There seems to be a fairly large opinion and experience base that suggests the laser printer and (specific) photographic paper products are not just better, but less expensive than "Press n Peel" products.
Regards,
John L. Males
Willowdale, Ontario
Canada
05 November 2007 20:14
05 November 2007 20:15 - 20:56 Find and fix board URL handing bug. jlm
Official Quasi Thread Researcher
Hi Chris,
Excellent approach on the MOSFET matching. I was thinking of using the DS18B20 device to measure the device temp on the heatsink. I have the serial bus devices and the DS18B20 and DS1820s to allow me to run the tests. I was also thinking of using a heatsink, but I did not think of running a number of devices at the same time. That latter point makes excellent sense. I was hoping that I could link up the temperature, voltage and current readings so they are all done at same time and logged. Then after the data is captured I could review it pick a stable operating point reading.
Quick question - is it best to run this test at the same rail voltage and bias current as the device will operate at or at a "choice" voltage I expect most of the playback will occur at? This of course affects the resistor value to set the current of the test.
Regards,
John L. Males
Willowdale, Ontario
Canada
05 November 2007 21:08
Official Quasi Thread Researcher
Excellent approach on the MOSFET matching. I was thinking of using the DS18B20 device to measure the device temp on the heatsink. I have the serial bus devices and the DS18B20 and DS1820s to allow me to run the tests. I was also thinking of using a heatsink, but I did not think of running a number of devices at the same time. That latter point makes excellent sense. I was hoping that I could link up the temperature, voltage and current readings so they are all done at same time and logged. Then after the data is captured I could review it pick a stable operating point reading.
Quick question - is it best to run this test at the same rail voltage and bias current as the device will operate at or at a "choice" voltage I expect most of the playback will occur at? This of course affects the resistor value to set the current of the test.
Regards,
John L. Males
Willowdale, Ontario
Canada
05 November 2007 21:08
Official Quasi Thread Researcher
Hi John,
A simpler way to go about this would be to attach a heater and sensor to the heat sink. Just set your temperature and it will stay there unless your combined dissipation causes the temperature to increase. Now all your readings are at a constant temperature. Scratch one variable. 😀
There is no need to change your source resistors. Just put the mosfet in a current feedback loop and now there is another variable gone. Set current though a common reference signal and each mosfet is controlled to that. 😀 😀
Now all you have to do is plot VG against set current and tabulate them.
Ain't life beautiful?
To answer your last question, I do tend to apply the actual rail voltage on the drain that the device will be working at. You can vary that as well, of course. Now you may have created a family of curves. Automate this and you have a highly accurate mosfet curve tracer. Silly accurate actually.
-Chris
A simpler way to go about this would be to attach a heater and sensor to the heat sink. Just set your temperature and it will stay there unless your combined dissipation causes the temperature to increase. Now all your readings are at a constant temperature. Scratch one variable. 😀
There is no need to change your source resistors. Just put the mosfet in a current feedback loop and now there is another variable gone. Set current though a common reference signal and each mosfet is controlled to that. 😀 😀
Now all you have to do is plot VG against set current and tabulate them.
Ain't life beautiful?
To answer your last question, I do tend to apply the actual rail voltage on the drain that the device will be working at. You can vary that as well, of course. Now you may have created a family of curves. Automate this and you have a highly accurate mosfet curve tracer. Silly accurate actually.
-Chris
Quasi,
I assume you have not started a new thread for your 30W Class A variant of your n-channel based amplifier designs?
If so I like to ask a couple simple questions:
1) Are the losses of Vrail vs output device voltage rail swing basically the same?
2) Could I scale the NMOS LTP/current mirror resistances the same as the 30W Class A for the same Vrail of 30V?
I know you said there are less complex designs for use with 25V transformers, but I would really like to use these smaller transformers as well for the NMOS.
Regards,
John L. Males
Willowdale, Ontario
Canada
13 November 2007 12:38
Official Quasi Thread Researcher
I assume you have not started a new thread for your 30W Class A variant of your n-channel based amplifier designs?
If so I like to ask a couple simple questions:
1) Are the losses of Vrail vs output device voltage rail swing basically the same?
2) Could I scale the NMOS LTP/current mirror resistances the same as the 30W Class A for the same Vrail of 30V?
I know you said there are less complex designs for use with 25V transformers, but I would really like to use these smaller transformers as well for the NMOS.
Regards,
John L. Males
Willowdale, Ontario
Canada
13 November 2007 12:38
Official Quasi Thread Researcher
Hi John,
The problem with the Nmos series is the Vds losses (about 4 - 5v)that are a charecteristic of this design. With higher voltage rails and class AB operation this is a minor issue, although the heatsinks will be a little warmer than a more efficient design. With lower rails however this loss becomes a significant percentage of the available voltage.
To use this design in class A mode further exacerbates the problem because of the additional heat mentioned before.
So the class A design posted on my web site is intended for a bipolar output stage, where the output losses a much smaller.
If you wanted to build a class A mosfet amp then the other mos design would be a better choice because the auxillary rail provides sufficient voltage drive eliminating the Vds problem.
http://www.diyaudio.com/forums/showthread.php?postid=759531#post759531
Cheers
Q
The problem with the Nmos series is the Vds losses (about 4 - 5v)that are a charecteristic of this design. With higher voltage rails and class AB operation this is a minor issue, although the heatsinks will be a little warmer than a more efficient design. With lower rails however this loss becomes a significant percentage of the available voltage.
To use this design in class A mode further exacerbates the problem because of the additional heat mentioned before.
So the class A design posted on my web site is intended for a bipolar output stage, where the output losses a much smaller.
If you wanted to build a class A mosfet amp then the other mos design would be a better choice because the auxillary rail provides sufficient voltage drive eliminating the Vds problem.
http://www.diyaudio.com/forums/showthread.php?postid=759531#post759531
Cheers
Q
Hi Quasi,
Thanks for your reply.
I was aware a NMOS design has an additional 4-5V loss vs a similar Bipolar design. I was aware of the percentage of the transformer secondary output loss would be about 50% at 30V rails. Like you, I was not happy about that, but that is just a fact of electron life. I also assumed the percentage would still be high, all be a tad less, for a Bipolar output, assuming a Class AB for both.
I inquired about your Class A variant in case my assumption about the percentage rail losses was incorrect. I am very familiar with the Class A heat and waste. I have avoided Class A designs even at 15-20 watts due to their heatsink requirements and losses in heat.
I know I cannot use a higher voltage for the driver/LTP stages in your NMOS350/500/200 design, and I suspect the same is true for your Brother of Quasi design. Perhaps I need to figure out how to adapt your NMOS design for a complimentary output device design which would allow me to use higher Vrail for the driver/LTP stages. The toroids I have at these lower voltages can easily have an additional winding added for the higher LTP/driver voltage. This seems to be the best compromise to keep as much of the quasi design as possible. If I do, maybe we should call it the Nephew of Quasi.
Regards,
John L. Males
Willowdale, Ontario
Canada
14 November 2007 02:40
Official Quasi Thread Researcher
Thanks for your reply.
I was aware a NMOS design has an additional 4-5V loss vs a similar Bipolar design. I was aware of the percentage of the transformer secondary output loss would be about 50% at 30V rails. Like you, I was not happy about that, but that is just a fact of electron life. I also assumed the percentage would still be high, all be a tad less, for a Bipolar output, assuming a Class AB for both.
I inquired about your Class A variant in case my assumption about the percentage rail losses was incorrect. I am very familiar with the Class A heat and waste. I have avoided Class A designs even at 15-20 watts due to their heatsink requirements and losses in heat.
I know I cannot use a higher voltage for the driver/LTP stages in your NMOS350/500/200 design, and I suspect the same is true for your Brother of Quasi design. Perhaps I need to figure out how to adapt your NMOS design for a complimentary output device design which would allow me to use higher Vrail for the driver/LTP stages. The toroids I have at these lower voltages can easily have an additional winding added for the higher LTP/driver voltage. This seems to be the best compromise to keep as much of the quasi design as possible. If I do, maybe we should call it the Nephew of Quasi.
Regards,
John L. Males
Willowdale, Ontario
Canada
14 November 2007 02:40
Official Quasi Thread Researcher
Regulated Front End Supply
Quasi, I would like to try out my amp based on your design, with regulated supply for the front end. Should I include the driver transistors in the higher supply line or leave them with the output stage power rails?
Have you tried a cascoded VAS stage?
How about using a mosfet like IRF610, 710 etc., for the VAS?
Different questions.....
Thanks,
Quasi, I would like to try out my amp based on your design, with regulated supply for the front end. Should I include the driver transistors in the higher supply line or leave them with the output stage power rails?
Have you tried a cascoded VAS stage?
How about using a mosfet like IRF610, 710 etc., for the VAS?
Different questions.....
Thanks,
Samuel,
If I may jump in here on one of your questions.
The the initial development stages of the NMOS had a split supply. One for the output devices and one for the input/driver stage. The input/driver stage used a regulated supply. quasi made a number of attempts to make the higher rail supply to the input/driver work, but to no avail.
Because of the challenges of using a split supply with this topology I would suspect using a regulated supply for the input/driver may pose some challenges. The challenge is not in designing the voltage/current requirements for the regulator, but the need to keep the regulated voltage very close to the unregulated supply of the output device stage. If there is a small difference between the regulated vs unregulated voltages then the problems quasi and others were trying to solve using a higher regulated input/driver stage will likely crop up again due to variations in mains supply voltages and sagging of the output device stage unregulated supply vs the regulated voltage.
If one uses a regulated output device stage supply it would eliminate the variances in the mains voltage, but may not address the sagging due to the impedance load changes on the output device stage.
I for one would be very interested in your solution to the challenge of a regulated supply for the input/driver stage, should you find one. I have tried using LTspice to experiment with different input/driver voltages and the results were not encouraging as quasi discovered in the early development of this design. The problem is I have some confidence issues with LTSpice and have not found another SPICE program I can use under Linux so far so I can evaluate the separate input/driver supply further. When I changed the value of R6 to some very rude value that should cause the LTP not to work, LTspice still showed the amplifier to work normally as if the R6 value was correct for the rail voltage being used. there was some other odd and inconsistent behaviour of LTspice that also caused me concerns.
Regards,
John L. Males
Willowdale, Ontario
Canada
14 November 2007 (11:50 -) 12:35
Official Quasi Thread Researcher
If I may jump in here on one of your questions.
The the initial development stages of the NMOS had a split supply. One for the output devices and one for the input/driver stage. The input/driver stage used a regulated supply. quasi made a number of attempts to make the higher rail supply to the input/driver work, but to no avail.
Because of the challenges of using a split supply with this topology I would suspect using a regulated supply for the input/driver may pose some challenges. The challenge is not in designing the voltage/current requirements for the regulator, but the need to keep the regulated voltage very close to the unregulated supply of the output device stage. If there is a small difference between the regulated vs unregulated voltages then the problems quasi and others were trying to solve using a higher regulated input/driver stage will likely crop up again due to variations in mains supply voltages and sagging of the output device stage unregulated supply vs the regulated voltage.
If one uses a regulated output device stage supply it would eliminate the variances in the mains voltage, but may not address the sagging due to the impedance load changes on the output device stage.
I for one would be very interested in your solution to the challenge of a regulated supply for the input/driver stage, should you find one. I have tried using LTspice to experiment with different input/driver voltages and the results were not encouraging as quasi discovered in the early development of this design. The problem is I have some confidence issues with LTSpice and have not found another SPICE program I can use under Linux so far so I can evaluate the separate input/driver supply further. When I changed the value of R6 to some very rude value that should cause the LTP not to work, LTspice still showed the amplifier to work normally as if the R6 value was correct for the rail voltage being used. there was some other odd and inconsistent behaviour of LTspice that also caused me concerns.
Regards,
John L. Males
Willowdale, Ontario
Canada
14 November 2007 (11:50 -) 12:35
Official Quasi Thread Researcher