Thank you Jan, and apologies to the Professor for being completely clueless about Belgian comics.
I did a bit of searching and found that English language Wikipedia has an article about Professor Tryphon Tournesol (here it is) whose name they translate into "Cuthbert Calculus".
Europeans may not have seen the naughty, erotic, 1970s-vintage, American comic strip called "The Adventures of Cuthbert Crotchpheasant" (example). It seems that Cuthbert is a name often chosen by comic strip artists, on both sides of the Atlantic.
I did a bit of searching and found that English language Wikipedia has an article about Professor Tryphon Tournesol (here it is) whose name they translate into "Cuthbert Calculus".
Europeans may not have seen the naughty, erotic, 1970s-vintage, American comic strip called "The Adventures of Cuthbert Crotchpheasant" (example). It seems that Cuthbert is a name often chosen by comic strip artists, on both sides of the Atlantic.
Because English is not my native language and because I have not learnt the few things that I know in electronic in school, but on the bench. Like many of us here, I believe.
All the people that had read my adventures know that I'm not a teacher, but some kind of an eccentric scientist.
Back to the real world and my life, your remark is funny because you are damn right. While I was not thinking to it when I chose this avatar, I was called "professor" in one of the company I was working in, and "Doctor Maboulette", by the boss of an other.
As a wink, I signed by this nickname the board driving the recording heads of our movies 16/35mm movies magnetic tape recorders. I had this crazy idea, instead of attacking them with some current sources or high impedance resistances, limiting the dynamic, to use the same (used) heads in the feedback path of a voltage amplifier. Once properly isolated from parasitic magnetic fields in a mumetal box, it was sounding very well (huge dynamic) and damn linear. Looking at the square waves was an interesting moment.
Let's look at the input stage. The first transistors are polarized by two current sources. Their current and temperature behavior will depend on those, and, because they are just emitters followers, with 100% of local feedback, we don't have to fear about their HFE disparities. The temp behavior has been fixed by the use of a normal diode in serial with the zener in the current sources references. It is known as working. This offers an over compensated temperature behavior. Notice that this stage is out of the feedback loop apart their parasitic capacitances, and offer a good separation of this loop from the world outside. And, as we can see, a negligible contribution to the overall distortion ;-)
Now, the second stage. If the VBE of the NPN/PNP and the PNP/NPN of the two stages were identical, we would have perfect balance of currents between the first and the second stage. Halas, it is not often the case.
Two situations can happen.
The VBE of the first stage transistor is higher than the second one: The current in the second will be higher than the one fixed by the current source, and the DC out multiplied by the gain of this second stage. Easy to fix, reducing the current from the current source to get to the second stage a given current necessary to fix the current in the VAS. No problem with less current in the first stage: not critical.
But, if the VBE of the first stage is lower than the one of the second, we are in a bad situation, the second stage will less or not conduct. Hence, the add of 2 extra resistances (R4/R74) in the emitters of the input transistor, to higher this voltage enough to make the second stage conducting. Varying the value of those resistances will tune the currents of the second stage.
The drawback we actually face is each time you change the current behavior of an half branch of one of our symmetrical 'pseudo diamond', it has an impact on the base currents/voltages, it means an impact on the other branch. Having two adjustable resistances that interact on each other is not easy to tune. More than this, if we wanted to perfectly balance the two stages to get identical currents on the four transistors, whe should have to change the current sources as well, that makes four adjustables, interacting on each others.
May-be there i a general rule that I don't know in the transistor pairs available on the market. Do all NPN/PNP VBE mismatches goes in the same sens ? I mean NPN having higher VBE than PNP ?
Are you talking about the schematic in post # 187? The input stage?
In general, in such circuits, one would couple the two current sources so that the same current is forced into both parts. I believe that is the case in that circuit. So which Vbe's are you meaning that upset things?
Where is connection 'x' going to, can't find it. Edit: found it.
BTW That schematic has the connection of the output zobel to gnd broken.
Jan
In general, in such circuits, one would couple the two current sources so that the same current is forced into both parts. I believe that is the case in that circuit. So which Vbe's are you meaning that upset things?
Where is connection 'x' going to, can't find it. Edit: found it.
BTW That schematic has the connection of the output zobel to gnd broken.
Jan
Now, you will have to figure out if I had chosen this comic 'character' because it fits mine, or if I make sometimes efforts to conform to my avatar's behaviors ;-)In the comics the protagonist shows some very stereotyped behaviour which often remarkably fits the poster
But do not deflect the original subject of this thread, that is not my person.
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I did not deflect, I answered a question from another person, and you could have seen that I already am back on the circuit.
This reaction is not a good way to prove you are NOT this character ;-) .
Jan
1- What part of my awkward explanation was not clear ? The VBE mismatch between PNP/NPN in each half branch.
If they always go the same sens, we could go for tuning the first stage emitter resistance in one half branch (the bottom one) and the current source emitter one in the other in order to equal the DC currents of the two half branch second transistors, that is the goal.
2- I did not care because it has no impact on CFA's gain loops. At least in sims.
My idea was to have-it in the board, by security, that we could populate or not.
I love to receive working boards with missing parts on it, thinking: "Oh, they have made some savings on my sample ?"
As it is not an industrial project, with a pre-serial to get all the experience, better to anticipate all eventual problems we can imagine. I don't remember if it was Mr. Murphy or Mr. Nyquist who said: "Amplifiers always oscillate." ;-).
Are you related to Frank Wolff ? ;-)
Do you mean Q1, Q5 as the 2nd stage?
Edit: it looks like you have 'painted yourself into a corner' with things like D15/R4/R73 and D16/R3/R74. This all depends on the specific Vbe/Vdiode and therefor very vulnerable for any small differences between parts. This will make it necessary to tweak each amp when build, none will be the same. Very difficult.
You have to look for a way to make this self-balancing or self compensating. You should not design a complex amp where a lot of the balance (maybe all of it) depends on the specific Vbe/Vdiode of some unpredictable value. That's asking for hell.
Jan
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As the labels ('Q1', 'Q2' etc.) of the transistors changes at each modifications in LT spice, I cannot answer this way. What I call first stages are the two transistors vertically aligned at the left of the schematic. The two emitters followers that drives the second stages (the ones with gain). Both make the input stage in a symmetrical diamond like topology.
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Just refer to the post where is the schematic you are referring to, or the name of the .asc file.. ... If you really want... to help.
Monsieur de La Palisse would not have said better.
I am curious, how many dynamically variable resistors, that respond to changes in the current of the second set of transistors would you need? And where would you place them or maybe an dynamically adjustable current source. I did some work on a Vbe tester some time ago, and I might be willing to subject my thoughts to this forum, if you will bear with me. In other words, I might have a POSSIBLE solution.
Jan, I do not intended to be desagreable. If you refer to post 187, the schottky and their two resistors bridges in the first stages emitters has been abandoned. Replaced with a single variable resistor. And it is not a reference full schematic, but an exploration one from spladski (that I missed, I don't know why).
We all do need help. But help means to provide solutions. Not to enlighten drawbacks we already know and try to solve.
On this sim schematic, you can see both offset need to be trimmed (V6) and that the R4, R74 resistances are not equal: this means an other trim depending of the VBEs. The main question waiting for a better solution.
And, as far temp simulation is in concern, as long as we try under around 20° LTPSICE fail to find the operating point. So I don't know what really happens. What we know is, as temperature increase, the current in output devices decrease.
What i can imagine is, while the current in the first stage is fixed by the current sources, the second is not conducting any more at very low temperature ? This means the base of Q7 is not conducting neither , hense no current in the output stage ? Or the contrary ? This need to be explored one way or an other. It is on my todo list. What I know is LTSPICE, in the range it is able to run with no error never show abnormal or dangerous current values and that they vary in the right direction.
Oh, Lord, yes.if you will bear with me. In other words, I might have a POSSIBLE solution.
Now having studied things, I see that Tournesol's instructions were wrong. The variable resistor is the other one of the divider. By adjusting the correct one, a solution has converged by using two diodes. This produces a system whereby the tempco can be altered. Some gain has been lost. Now investigating if one diode is feasible.
Looking deeper, concentrating on the temp behavior, I made previously a big mistake. Due to the fact that LTPICE is so long to simulate in trans if we want to escape the time needed for everything to be stabilised.
No, it do not goes in the right direction, on the contrary and tempco need yet to be solved. Not something so difficult or affraiting.
And, as it is based on our VBE problem, let's concentratie on this first.
I wonder why I made this error in interpretation, while I was sure to had verified previously. My bad. Nobody's perfect ;-)
I am verifying several ideas at this moment.
EDIT. I verified again: 95 mA in power fets @ 50°, 104 @ 20°. 106 @ 0+ was-i not mistaken ?
This is my actual file:
Actual file I was referring to:
spladski, I understand now the differences of our results. I use, of course the same transistor pairs in stage 1&2 of the input with a negative tempco: 2N54401 2N5551C . You: 2SC in the first stage and BC etc. in the second stage with a positive one.
The V5 in LTspice IV checks out. You don't need to run a long sim for temp. Turn off all extraneous elements. Not sure where this leaves device selection. The 2N5401 and 2N5551 both have neg tempco for vbe and were chosen for tolerance to device change. Intolerance to device change goes hand in hand with intolerance to temp. So although the sim is OK, the breadboard will be needed to prove it.
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